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january 2005 i ? 2005 actel corporation see actel?s website for the latest version of the datasheet. proasic3 flash family fpgas features and benefits high capacity ? 30 k to 1 million system gates up to 144 kbits of true dual-port sram up to 288 user i/os reprogrammable flash technology 130-nm, 7-layer metal (6 copper), flash-based cmos process live-at-power-up level 0 support single-chip solution retains programmed design when powered off on-chip user nonvolatile memory 1 kbit of flashrom (from) performance 150+ mhz internal system performance with 3.3 v, 66 mhz 64-bit pci (except a3p030) up to 350 mhz external system performance in-system programming (isp) and security secure isp using on-chip 128-bit aes decryption via jtag (ieee1532-compliant) (except a3p030) flashlock? to secure fpga contents low power 1.5 v core voltage for low power support for 1.5-v-only systems low-impedance flash switches high-performance routing hierarchy segmented, hierarchical routing and clock structure ultra-fast local and long-line network enhanced high-speed, very long-line network high-performance, low-skew global network architecture supports ultra-high utilization advanced i/o 700 mbps ddr, lvds-capable i/os (a3p250 and above) 1.5 v, 1.8 v, 2.5 v, and 3.3 v mixed-voltage operation bank-selectable i/o voltages ? up to 4 banks per chip single-ended i/o standards: lvttl, lvcmos 3.3 v / 2.5 v / 1.8 v / 1.5 v, 3.3 v pci / 3.3 v pci-x (except a3p030), and lvcmos 2.5 v / 5.0 v input differential i/o standards: lvpecl and lvds (a3p250 and above) i/o registers on input, output, and enable paths hot-swappable i/os (a3p030 only) programmable output slew rate and drive strength weak pull-up/down ieee1149.1 (jtag) boundary-scan test pin-compatible packages ac ross the proasic3 family clock conditioning circ uit (ccc) and pll (except a3p030) six ccc blocks total, one with an integrated pll flexible phase shift, multiply/divide, and delay capabilities wide input frequency range (1.5 mhz to 350 mhz) srams and fifos (except a3p030) variable-aspect ratio 4,608-bi t ram blocks (x1, x2, x4, x9, x18 organizations available) true dual-port sram (except x18) 24 sram and fifo configurations with synchronous operation up to 350 mhz programmable embedded fifo control logic ? table 1 proasic3 product family a3p030 A3P060 a3p125 a3p250 a3p400 a3p600 a3p1000 system gates 30 k 60 k 125 k 250 k 400 k 600 k 1 m versatiles (d-flip-flops) 768 1,536 3,072 6,144 9,216 13,824 24,576 ram kbits (1,024 bits) ? 18 36 36 54 108 144 4,608 bit blocks ? 4 8 8 12 24 32 flashrom (from) bits 1 k 1 k 1 k 1 k 1 k 1 k 1 k secure (aes) isp ? yes yes yes yes yes yes integrated pll in cccs ? 1 1 1 1 1 1 versanet globals 1 6181818 18 18 18 i/o banks 2 2 2 4 4 4 4 maximum user i/os 81 96 133 157 194 227 288 package pins qfn vqfp tqfp pqfp fbga qn132 vq100 vq100 tq144 fg144 vq100 tq144 pq208 fg144 vq100 pq208 fg144, fg256 pq208 fg144, fg256, fg484 pq208 fg144, fg256, fg484 pq208 fg144, fg256, fg484 notes: 1. six chip (main) and three quadrant global networks are available for A3P060 and above. 2. for higher densities and support of additional features, refer to the proasic3e flash fpgas datasheet. advanced v0.2
proasic3 flash family fpgas ii advanced v0.2 i/os per package ordering information package a3p030 A3P060 a3p125 a3p250 a3p400 a3p600 a3p1000 single-ended i/o single-ended i/o single-ended i/o single-ended i/o differential i/o pairs single-ended i/o differential i/o pairs single-ended i/o differential i/o pairs single-ended i/o differential i/o pairs qn132 81 ? ? ? ? ? ? ? ? ? vq1007971716813 ? ? ? ? ? tq144 ? 91 100 ? ? ? ? ? ? ? ? pq208 ? ? 133 151 34 151 33 154 35 154 35 fg144 ? 96 97 97 24 97 24 97 24 97 24 fg256 ? ? ? 157 38 178 38 179 45 179 45 fg484 ? ? ? ? ? 194 38 227 56 288 68 notes: 1. each used differential i/o pair reduces the number of single-ended i/os available by two. 2. fg256 and fg484 are footprint-compatible packages. 3. advanced informatio n subject to change. note: *dc and switching characterist ics for ?f speed grade target s based only on simulation. the characteristics provided for ?f speed grade are subject to change after esta blishing fpga specifications. some restrictions might be added and will be reflected in future revisions of this document . the ?f speed grade is only supported in commercial temperatur e range. figure 1 ordering information speed grade blank = standard 1 = 15% faster than standard 2 = 25% faster than standard f = 20% slower than standard* a3p1000 fg _ part number 1 package type vq = very thin quad flat pack (0.5 mm pitch) qn = quad flat no leads (0.5 mm pitch) tq = thin quad flat pack (0.5 mm pitch) 144 i package lead count application (ambient temperature range) blank = commercial (0?c to +70?c) i = industrial (-40?c to +85?c) pp = pre-production es = engineering silicon (room temperature only) 30,000 system gates a3p030 = 60,000 system gates A3P060 = 125,000 system gates a3p125 = 250,000 system gates a3p250 = 400,000 system gates a3p400 = 600,000 system gates a3p600 = 1,000,000 s y stem gates a3p1000 = pq = plastic quad flat pack (0.5 mm pitch) fg = fine pitch ball grid array (1.0 mm pitch)
proasic3 flash family fpgas advanced v0.2 iii temperature grade offerings speed grade and temperature grade matrix contact your local actel represen tative for device availability ( http://www.actel.com/con tact/offices/index.html ). package a3p030 A3P060 a3p125 a3p250 a3p400 a3p600 a3p1000 qn132c, i?????? vq100 c, ic, ic, ic, i ? ? ? tq144 ? c, i c, i ? ? ? ? pq208 ? ? c, ic, ic, ic, ic, i fg144 ? c, ic, ic, ic, ic, ic, i fg256 ? ? ? c, ic, ic, ic, i fg484 ????c, ic, ic, i note: c = commercial temperature range: 0c to 70c ambient i = industrial temperature range: ?40c to 85c ambient ?f 3 std. ?1 ?2 c ???? i ? ??? notes: 1. c = commercial temperature range: 0c to 70c ambient 2. i = industrial temperature range: ?40c to 85c ambient 3. dc and switching characteri stics for ?f speed grade targets based only on simulation. the characteristics provided for ?f speed grade are subject to change after esta blishing fpga specifications. some restrictions might be added and will be reflected in future revisions of th is document. the ?f speed grade is only supported in commercial temperature range.
iv advanced v0.2 table of contents proasic3 flash family fpgas introduction and overview general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 related documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 device architecture introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-46 software tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-47 programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-47 security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-47 isp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-48 dc and switching characteristics general specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 calculating power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 user i/o characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 versatile characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41 global resource characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-45 embedded sram and fifo characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-50 embedded from characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-59 jtag 1532 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-60 package pin assignments 132-pin qfn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 -1 100-pin vqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 -2 144-pin tqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 -6 208-pin pqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 1 144-pin fbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22 256-pin fbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-27 484-pin fbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-40 datasheet information datasheet categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 international traffic in arms regulati ons (itar) and export administration regulations (ear) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
proasic3 flash family fpgas advanced v0.2 1-1 introduction and overview general description proasic3, the third-generation family of actel flash fpgas, offers performance, density, and features beyond those of the proasic plus ? family. the nonvolatile flash technology gives proasic3 devices the advantage of being a secure, low-power, single-chip solution that is live at power-up. proasic3 is reprogrammable and offers time-to-market benefits at an asic-level unit cost. these features enable designers to create high-density systems using existing asic or fpga design flows and tools. proasic3 devices offer 1 kbit of on-chip, user nonvolatile flashrom (from) memory storage as well as clock conditioning circuitry based on an integrated phase- locked loop (pll). the a3p030 device has no pll or ram support. proasic3 devices have up to 1 million system gates, supported with up to 144 kbits of true dual-port sram and up to 288 user i/os. flash advantages reduced cost of ownership advantages to the designer extend beyond low-unit cost, performance, and ease of use. unlike sram-based fpgas, the flash-based proasic3 devices allow for all functionality to be live at power-up; no external boot prom is required. on-board security mechanisms prevent access to all the programming information and enable secure remote updates of the fpga logic. designers can perform secure remote in-system reprogramming to support future design iterations and field upgrades with confidence that valuable intellectual property (ip) cannot be compromised or copied. secure isp can be performed using the industry-standard aes algorithm. the proasic3 family device architecture mitigates the need for asic migration at higher user volumes. this makes the proa sic3 family a cost-effective asic replacement solution, es pecially for applications in the consumer, networking/communications, computing, and avionics markets. security the nonvolatile, flash-based proasic3 devices require no boot prom, so there is no vu lnerable external bitstream that can be easily copied. pr oasic3 devices incorporate flashlock, which provides a unique combination of reprogrammability and design security without external overhead, advantages th at only an fpga with nonvolatile, flash programming can offer. proasic3 devices utilize a 128-bit flash-based lock and a separate aes key to secure programmed intellectual property and configuration data. in addition, all from data in the proasic3 devices can be encrypted prior to loading, using the industry-leading aes-128 (fips192) bit block cipher encryption stan dard. the aes standard was adopted by the national institute of standards and technology (nist) in 2000, and replaces the 1977 des standard. proasic3 devices have a built-in aes decryption engine and a flash-based aes key that make them the most comprehensive programmable logic device security solution available today. proasic3 devices with aes-based security allow for secure, remote field updates over public networks such as the internet, and ensure that valuable ip remains out of the hands of system overbuilders, system cloners, and ip thieves. the contents of a programmed proasic3 device cannot be read back, although secure design verification is possible. security, built into the fpga fabric, is an inherent component of the proasic3 family. the flash cells are located beneath seven metal layers, and many device design and layout techniques have been used to make invasive attacks extremely difficult. proasic3, with flashlock and aes security, is unique in being highly resistant to both invasive and noninvasive attacks. your valuable ip is protected and secure, making remote isp possible. a proasic3 device provides the most impenetrable security for programmable logic designs.
proasic3 flash family fpgas 1-2 advanced v0.2 single chip flash-based fpgas store the configuration information in on-chip flash cells. once programmed, the configuration data is an inherent part of the fpga structure and no external co nfiguration data needs to be loaded at system power-up (unlike sram-based fpgas). therefore, flash-based proasic3 fpgas do not require system configuration com ponents such as eeproms or microcontrollers to load the device configuration data. this reduces bill-of-materials costs and printed circuit board (pcb) area, and incr eases security and system reliability. live at power-up actel?s flash-based proasic3 devices support level 0 of the live-at-power-up classification standard, hence helping in system components initialization, executing critical tasks before the pr ocessor wakes up, setup and configure memory blocks, clock generation, and bus activity management. the live-at-power-up feature of flash-based proasic3 devices greatly simplifies total system design and reduces total system cost, often eliminating the need for complex programmable logic device (cpld) and clock genera tion pll that are used for this purpose in a system. in addition, glitches and brownouts in system po wer will not corrupt the proasic3 device?s flash configuration, and unlike sram- based fpgas, the device will not have to be reloaded when system power is re stored. this enables the reduction or complete removal of the configuration prom, expensive voltage monitor, brownout detection, and clock generator devices from the pcb design. flash- based proasic3 devices simplify total system design, and reduce cost and design risk, while increasing system reliability and improving sy stem initialization time. firm errors firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere, strike a configuration cell of an sram fpga. the energy of the collision can change the stat e of the conf iguration cell and thus change the logic, routing, or i/o behavior in an unpredictable way. these errors are impossible to prevent in sram fpgas. the consequence of this type of error can be a complete system failure. firm errors do not exist in the configuration memory of proasic3 flash- based fpgas. once it is programmed, the flash cell configuration element of proasic3 fpgas cannot be altered by high-energy ne utrons and is therefore immune to them. recoverable (or soft) errors occur in the user data sram of all fpga devices. these can easily be mitigated by using error detection and correction (edac) circuitry built into the fpga fabric. low power flash-based proasic3 devices exhibit power characteristics similar to an asic, making them an ideal choice for power-sensitive applications. proasic3 devices have only a very limited pow er-on current surge, and no high-current transition period, both of which occur on many fpgas. proasic3 devices also have low dynamic power consumption to further maximize power savings. advanced flash technology the proasic3 family offers many benefits, including nonvolatility and reprogr ammability through an advanced flash-based, 130- nm lvcmos process with seven layers of metal. standard cmos design techniques are used to implement logic and control functions. the combination of fine granularity, enhanced flexible routing resources, and abund ant flash switches allows for very high logic utiliz ation without compromising device routability or performance. logic functions within the device are interconne cted through a four-level routing hierarchy. advanced architecture the proprietary proasic3 architecture provides granularity comparable to standard-cell asics. the proasic3 device consists of five distinct and programmable archit ectural features ( figure 1-1 on page 1-3 and figure 1-2 on page 1-3 ): dedicated flashrom (from) memory dedicated sram/fifo memory 1 extensive clock conditioning circuitry (ccc) and plls 1 advanced i/o structure fpga versatiles the fpga core consists of a sea of versatiles. each versatile can be configured as a three-input logic function or a d-flip-flop (with or without enable) or latch by programming the appropriate flash switch interconnections. the versatilit y of the proasic3 core tile as either a three-input look -up-table (lut) equivalent or a d-flip-flop/latch with enable allows for efficient use of the fpga fabric. the versatile capability is unique to the actel proasic families of fl ash-based fpgas. versatiles are connected with any of the four levels of routing hierarchy. flash switches ar e distributed throughout the device to provide nonvolatile, reconfigurable interconnect programming. maximum core utilization is possible for virtually any design. in addition, extensive on-chip programming circuitry allows for rapid, single-voltage (3.3 v) programming of the proasic3 devices via an ieee1532 jtag interface. 1. the a3p030 device does not support pll and sram.
proasic3 flash family fpgas advanced v0.2 1-3 note: *not supported by a3p030. figure 1-1 proasic3 device architecture overview with two i/o banks (a3p030, A3P060, a3p125) figure 1-2 proasic3 device architecture o verview with four i/o banks (a3p250, a3p400, a3p600, and a3p1000) ram block 4,608-bit dual-port sram or fifo block* versatile ccc i/os isp aes decryption* user nonvolatile flashrom (from) charge pumps bank 0 bank 1 bank 1 bank 0 bank 0 bank 1 ram block 4,608-bit dual-port sram or fifo block (a3p600 and a3p1000) ram block 4,608-bit dual-port sram or fifo block versatile ccc i/os isp aes decryption user nonvolatile flashrom (from) charge pumps bank 0 bank 3 bank 3 bank 1 bank 1 bank 2
proasic3 flash family fpgas 1-4 advanced v0.2 user nonvolatile flashrom (from) actel proasic3 devices have 1 kbit of on-chip, user- accessible, nonvolatile flas hrom (from). the from can be used in diverse system applications such as: internet protocol addressing (wireless or fixed) system calibration settings device serialization an d/or inventory control subscription-based business models (for example, set-top boxes) secure key storage for secure communications algorithms asset management/tracking date stamping version management the from is written using the standard proasic3 ieee1532 jtag programming interface. the core can be individually programmed (erased and written) and on- chip aes decryption can be used selectively to securely load data over public netw orks (except in the a3p030 device), such as security keys stored in the from for a user design. the from can be programmed via the jtag programming interface, and its contents can be read back either through the jtag programming interface or via direct fpga core addressing. note that the from can only be programmed from the jtag interface, and cannot be programmed from the internal logic array. the from is programmed as 8 banks of 128 bits; however, reading is performed on a random byte-by- byte basis. a 7-bit address from the fpga core defines which of the 8 banks and wh ich of the 16 bytes within that bank are being read. the three msbs of the from address determine the bank and the four lsbs of the from address define the byte. the actel proasic3 development software solutions, libero ? integrated design environment (ide) and designer version 6.1 or later, have extensive support for the from memory. one such feature is auto-generation of sequential programming files for applications requiring a unique serial number in each part. the second part allows the inclusion of static data for system version control. data for the from can be generated quickly and easily using actel libero ide and designer software tools. comprehensive programming file support is also included to allow for easy programming of large numbers of parts wi th differing from contents. sram and fifo proasic3 devices (except in the a3p030 device) have embedded sram blocks along the north and south sides of the device. each variable -aspect-ratio sram block is 4,608 bits in size. available memory configurations are 256x18, 512x9, 1kx4, 2kx2, or 4kx1 bits. the individual blocks have independent read and write ports that can be configured with different bit widths on each port. for example, data can be sent through a four-bit port and read as a single bitstream . the embedded sram blocks can be initialized via the device jtag port (rom emulation mode), using the ujtag macro (except for the a3p030 device). refer to the application note, ujtag in proasic3/e devices , for more details. in addition, every sram block has an embedded fifo control unit. the control unit allows the sram block to be configured as a synchronous fifo without using additional core versatiles. the fifo width and depth are programmable. the fifo also features programmable almost-empty (aempty) and almost-full (afull) flags in addition to the normal empty and full flags. the embedded fifo control unit contains the counters necessary for the generation of the read and write address pointers. the embedd ed sram/fifo blocks can be cascaded to create larger configurations. pll and clock conditioning circuitry (ccc) proasic3 devices provide designers with very flexible clock conditioning capabilities. each member of the proasic3 family contains six cccs. one ccc (center west side) has a phase-locked loop (pll) ( figure 2-10 on page 2-10 ). the a3p030 does not have a pll. the six ccc blocks are located in the four corners and the centers of the east and west sides. all six ccc blocks are usable ; the four corner cccs and the east ccc allow simple clock delay operations as well as clock spine access (refer to the "clock conditioning circuits" section on page 2-13 for more information). the inputs of the six ccc bloc ks are accessible from the fpga core or from one of se veral i/o inputs located near the ccc that have dedicated connections to the ccc block.
proasic3 flash family fpgas advanced v0.2 1-5 the ccc block has the following key features: wide input frequency range (f in_ccc ) = 1.5 mhz to 350 mhz output frequency range (f out_ccc ) = 0.75 mhz to 350 mhz clock delay adjustment via programmable and fixed delays from ?7.56 ns to +11.12 ns two programmable delay types; refer to figure 2- 17 on page 2-17 , table 2-4 on page 2-18 , and the "features supported on every i/o" section on page 2-29 for more information. clock skew minimization clock frequency synthesis (for pll only) additional ccc specifications: internal phase shift = 0, 90, 180, and 270. output phase shift depends on the output divider configuration (for pll only). output duty cycle = 50% 1.5% or better (for pll only) low output jitter: worst case < 2.5% * clock period peak-to-peak period jitter (for pll only) ? 70 ps at 350 mhz ? 90 ps at 100 mhz ? 180 ps at 24 mhz maximum acquisition time = 150 s (for pll only) low power consumption of 5 mw exceptional tolerance to input period jitter ? allowable input jitter is up to 1.5 ns (for pll only) four precise phases; maximum misalignment between adjacent phases of 40 ps * (350 mhz / f out_ccc ) (for pll only) global clocking proasic3 devices have extensive support for multiple clocking domains. in addition to the ccc and pll support described above, there is a comprehensive global clock distribution network. each versatile input and output port has access to nine versanets: six chip (main) and three quadrant global networks ( figure 2-10 on page 2-10 ). the versanets can be driven by the ccc or directly accessed from the core via multiplexers (muxes). the versanets can be used to distribute low-skew clock signals or for rapid distribution of high-fanout nets. i/os with advanced i/o standards the proasic3 family of fpgas features a flexible i/o structure, supporting a range of voltages (1.5 v, 1.8 v, 2.5 v, and 3.3 v). in all, proasic3 fpgas support many different i/o standards, both single-ended and differential. for more information, see table 2-19 on page 2-42 . the i/os are organized into banks, with two or four banks per device. refer to table 2-18 on page 2-42 for details on i/o bank configurat ion. the configuration of these banks determines the i/o standards supported (see table 2-18 on page 2-42 for more information). each i/o module contains several input, output, and enable registers ( figure 2-23 on page 2-30 ). these registers allow the implemen tation of the following: single-data-rate applications double-data-rate applications ? ddr lvds i/o for point-to-point communications versatiles the proasic3 core consists of versatiles, which have been enhanced over the proasic plus core tiles. the proasic3 versatile su pports the following: all three-input logic functions ? lut-3 equivalent latch with clear or set d-flip-flop with clear or set enable d-flip-flop with clear or set refer to figure 1-3 for versatile configurations. for more information about versatiles, refer to the "versatile" section on page 2-2 . figure 1-3 versatile configurations x1 y x2 x3 lut-3 data y clk enable clr d-ff data y clk clr d-ff lut-3 equivalent d-flip-flop with clear or set enable d-flip-flop with clear or set
proasic3 flash family fpgas 1-6 advanced v0.2 related documents application notes in-system programming (isp) in proasic3/e using flashpro3 http://www.actel.com/doc uments/pa3_e_isp_an.pdf optimal usage of global network spines in proasic plus devices http://www.actel.com/docum ents/paplus_spines_an.pdf proasic3/e flashrom (from) http://www.actel.com/doc uments/pa3_e_from_an.pdf proasic3/e security http://www.actel.com/docum ents/pa3_e_security_an.pdf proasic3/e sram/fifo blocks http://www.actel.com/documen ts/pa3_e_sramfifo_an.pdf programming a proasic3/e using a microprocessor http://www.actel.com /documents/pa3_e_microprocessor_an.pdf ujtag applications in proasic3/e devices http://www.actel.com/docum ents/pa3_e_ujtag_an.pdf using ddr for proasic3/e devices http://www.actel.com/doc uments/pa3_e_ddr_an.pdf using global resources in actel proasic3/e devices http://www.actel.com/docum ents/pa3_e_global_an.pdf for additional proasic3 application notes, go to http://www.actel.com/techdocs/appnotes/products.aspx . user?s guides actgen core reference guide http://www.actel.com/docum ents/gen_refguide.pdf designer?s user?s guide http://www.actel.com/doc uments/designerug.pdf proasic3/e macro library guide http://www.actel.com/doc uments/pa3_libguide.pdf
proasic3 flash family fpgas advanced v0.2 2-1 device architecture introduction flash technology advanced flash switch unlike sram fpgas, the proasi c3 family uses a live-on- power-up isp flash switch as its programming element. flash cells are distributed throughout the device to provide nonvolatile, reconfigurable programming to connect signal lines to the appropriate versatile inputs and outputs. in the flash switch, two transistors share the floating gate, which stores the programming information ( figure 2-1 ). one is the sensing transistor, which is only used for writ ing and verification of the floating gate voltage. th e other is the switching transistor. the latter is used to connect or separate routing nets, or to configure versatile logic. it is also used to erase the floating gate. dedicated high- performance lines are connected as required using the flash switch for fast, low-skew, global signal distribution throughout the devi ce core. maximum core utilization is possible for virtually any de sign. the use of the flash switch technology also remo ves the possibility of firm errors, which are increasin gly common in sram-based fpgas. figure 2-1 proasic3 flash-based switch sensing switching switch in switch out word floating gate
proasic3 flash family fpgas 2-2 advanced v0.2 device overview the proasic3 device family consists of five distinct programmable archit ectural features ( figure 2-2 and figure 2-3 on page 2-3 ): fpga fabric/core (versatiles) routing and clock resources (versanets) flashrom (from) memory dedicated sram/fifo memory (except a3p030) advanced i/o structure core architecture versatile the proprietary proasic3 fa mily architecture provides granularity comparable to gate arrays. the proasic3 device core consists of a s ea-of-versatiles architecture. as illustrated in figure 2-4 on page 2-4 , there are four inputs in a logic versatile cell, and each versatile can be configured using the appropriate flash switch connections: any three-input logic function latch with clear or set d-flip-flop with clear or set enable d-flip-flop with clear or set (on a fourth input) versatiles can flexibly map the logic and sequential gates of a design. the inputs of the versatile can be inverted (allowing bubble pushing), and the output of the tile can connect to high-speed, very-long-line routing resources. versatiles and larger function s are connected with any of the four levels of routing hierarchy. when the versatile is used as an enable d-flip-flop, the set/clr is supported by a f ourth input. the fourth input is routed to the core cell over the versanet (global) network. the set/clr signal can only be routed to this fourth input over the versanet (globa l) network. however, if in the user design, the set/clr signal is not routed over the versanet network, a comp ile warning message will be given and the intended logic function will be implemented by two vers atiles instead of one. the output of the versatile is f2 when the connection is to the ultra-fast local lines, or yl when connection is to the efficient long-lines or very-long-lines resources. note: *not supported by a3p030. figure 2-2 proasic3 device architecture overview with two i/o banks (a3p030, A3P060, a3p125) ram block 4,608-bit dual-port sram or fifo block* versatile ccc i/os isp aes decryption* user nonvolatile flashrom (from) charge pumps bank 0 bank 1 bank 1 bank 0 bank 0 bank 1
proasic3 flash family fpgas advanced v0.2 2-3 figure 2-3 proasic3 device architecture overview with four i/o banks (a3p250, a3p400, a3p600, a3p1000) ram block 4,608-bit dual-port sram or fifo block (a3p600 and a3p1000) ram block 4,608-bit dual-port sram or fifo block versatile ccc i/os isp aes decryption user nonvolatile flashrom (from) charge pumps bank 0 bank 3 bank 3 bank 1 bank 1 bank 2
proasic3 flash family fpgas 2-4 advanced v0.2 note: *this input can only be connected to the global clock distribution network. figure 2-4 proasic3 core versatile switch (flash connection) ground via (hard connection) legend: y pin 1 0 1 0 1 0 1 0 1 data x3 clk x2 clr/ enable x1 clr xc* f2 yl
proasic3 flash family fpgas advanced v0.2 2-5 array coordinates during many place-and-rout e operations in the actel designer software tool, it is possible to set constraints that require array coordinates. table 2-1 is provided as a reference. the array coordina tes are measured from the lower left (0, 0). they can be used in region constraints for specific logic groups/blocks, designated by a wildcard, and can contain core cells, memories, and i/os. table 2-1 provides array coordinates of core cells and memory blocks. since the i/o coordinate system changes depending on the die/package combinatio n, it is not listed in table 2-1 . the designer chipplanner tool provides array coordinates of all i/o locations. i/o and cell coordinates are used for placement co nstraints. however, i/o placement is easier by package pin assignment. figure 2-5 illustrates the array coordinates of an a3p600 device. for more information on how to use array coordinates for region/placem ent constraints, see the designer user's guide or online help (available in the software) for proasic3 software tools. table 2-1 proasic3 array coordinates versatiles memory rows all min. max. bottom top min. max. device x y x y (x, y) (x, y) (x, y) (x, y) a3p030???????? A3P060 3 2 66 25 none (3, 26) (0, 0) (69, 29) a3p125 3 2 130 25 none (3, 26) (0, 0) (133, 29) a3p250 3 2 130 49 none (3, 50) (0, 0) (133, 53) a3p400 3 2 194 49 none (3, 50) (0, 0) (197, 53) a3p600 3 4 194 75 (3,2) (3, 76) (0, 0) (197, 79) a3p1000 3 4 258 99 (3,2) (3, 100) (0, 0) (261, 103) note: the vertical i/o tile coordi nates are not shown. west side c oordinates are {(0, 2) to (2, 2)} to {(0, 77) to (2, 77)}; east sid e coordinates are {(195, 2) to (197, 2)} to {(195, 77) to (197, 77)}. figure 2-5 array coordinates for a3p600 top row (5, 1) to (168, 1) bottom row (7, 0) to (165, 0) top row (192, 1) to (169, 1) i/o tile memory blocks memor y blocks memory blocks ujtag flashrom top row (7, 79) to (189, 79) bottom row (5, 78) to (192, 78) i/o tile (3, 77) (3, 76) memory blocks (3, 3) (3, 2) versatile (core) (3, 75) versatile (core) (3, 4) (0, 0) (197, 0) (194, 2) (194, 3) (194, 4) versatile(core) (194, 75) versatile (core) (197, 79) (194, 77) (194, 76) (0,79) (197, 1)
proasic3 flash family fpgas 2-6 advanced v0.2 routing architecture routing resources the routing structure of proasic3 devices is designed to provide high performance through a flexible four-level hierarchy of routing resources: ultra-fast local resources, efficient long-line resources, high-speed, very-long-line resources, and the high-perfo rmance versanet networks. the ultra-fast local resources are dedicated lines that allow the output of each versatile to connect directly to every input of the eight surrounding versatiles ( figure 2-6 ). the exception to this is that th e set/clr input of a versatile configured as a d-type flip-f lop is driven only by the versatile global network. the efficient, long-line resources provide routing for longer distances and higher fanout connections. these resources vary in length (spa nning 1, 2, or 4 versatiles), run both vertically and horizontally, and cover the entire proasic3 device ( figure 2-7 on page 2-7 ). each versatile can drive signals onto the efficient long-line resources, which can access every input of every versatile. active buffers are inserted automatically by routing software to limit the loading effects. the high-speed, very-long-line resources, which span the entire device with minimal delay, are used to route very long or high-fanout nets: le ngth +/?12 versatiles in the vertical direction and length +/?16 in the horizontal direction from a given core versatile ( figure 2-8 on page 2-8 ). very long lines in proasic3 devices have been enhanced over those in prev ious proasic families. this provides a significant performance boost for long-reach signals. the high-performance versan et global networks are low-skew, high-fanout nets that are accessible from external pins or from internal logic ( figure 2-9 on page 2-9 ). these nets are typically used to distribute clocks, resets, and other high-fanout nets requiring minimum skew. the versanet networks are implemented as clock trees, and signals can be introduced at any junction. these can be employed hierarchically with signals accessing every input on all versatiles. note: input to the core cell for the d-flip-flop set and reset is only available via the versanet global network connection. figure 2-6 ultra-fast local lines connected to the eight n earest neighbors l l l l l l inputs output ultra-fast local lines (connects a versatile to the adjacent versatile, i/o buffer, or memory block) l ll long lines
proasic3 flash family fpgas advanced v0.2 2-7 figure 2-7 efficient long-line resources l lllll l l llll l lllll l lllll l lllll versatile spans one versatile spans two versatiles spans four versatiles spans one versatile spans two versatiles spans four versatiles logic versatile
proasic3 flash family fpgas 2-8 advanced v0.2 figure 2-8 very-long-line resources high-speed, very-long-line resources pad ring pad ring i/o ring i/o ring pad ring 16x12 block of versatiles sram
proasic3 flash family fpgas advanced v0.2 2-9 clock resources (versanets) proasic3 devices offer powerful and flexible control of circuit timing through the use of analog circuitry. each chip has up to six cccs. the west ccc also contains a phase-locked loop (pll) core , delay lines, phase shifter (0, 90, 180, 270), and clock multiplier/dividers. each ccc has all the circuitry needed for the selection and interconnection of inputs to the versanet global network. the east and west cccs each have access to three versanet global lines on each side of the chip (six total lines). advantages of the versanet approach one of the architectural benefits of proasic3 is the set of powerful and low-delay versanet global networks. proasic3 offers six chip (main) global networks that are distributed from the center of the fpga array ( figure 2-9 ). in addition, proasic3 device s have three regional globals in each of the four chip quadr ants. each core versatile has access to nine global networ k resources: three quadrant and six chip (main) global networks, and a total of 18 globals on the device. each of these networks contain spines and rows that reach all the versatiles in the quadrants ( figure 2-10 on page 2-10 ). this flexible versanet global network architec ture allows users to map up to 144 different internal/external clocks in a proasic3 device. details on the versa net networks are given in table 2-2 on page 2-10 . the flexible use of the proasic3 versanet global network allows the designer to address several design requirements. us er applications that are clock-resource-intensive can ea sily route external or gated internal clocks using versanet global routing networks. designers can also drasticall y reduce delay penalties and minimize resource usage by mapping critical, high-fanout nets to the versanet global network. in a3p030 devices, all six vers anets come from the north edge of the fpga fabric. the a3p030 does not support the versanet global network concept of top and bottom spines due to the limited ga te density of this part. note: not applicable to the a3p030 device. figure 2-9 overview of proasic3 ve rsanet global network quadrant global pads top spine bottom spine pad ring pad ring pad ring i/o ring i/o ring chip (main) global pads spine-selection tree mux global pads high-performance versanet global network main (chip) global networ k global spine global ribs
proasic3 flash family fpgas 2-10 advanced v0.2 versanet global networks and spine access the proasic3 architecture contains nine segmented global networks that can access all the versatiles, sram memory, and i/o tiles on the proasic3 device. these versanet global networks of fer fast, low-skew routing resources for high-fanout nets, including clock signals. in addition, these highly-segment ed global networks offer users the flexibility to creat e low-skew local networks using spines for up to 144 in ternal/external clocks (in an a3p1000 device) or other high -fanout nets in proasic3 devices. optimal usage of these low-skew networks can result in significant improv ement in design performance on proasic3 devices. the nine spines available in a vertical column reside in global networks with two separate regions of scope: the quadrant global network, wh ich has three spines, and the chip (main) global network, which has six spines. there are four quadrant gl obal network regions per device ( figure 2-10 ). the spines are the vertical branches of the global network tree, shown in figure 2-11 on page 2-11 . each spine in a vertical column of a chip (main) global network is further divided into two spine segments: one in the top and one in the bottom half of the die. top and note: this does not apply to the a3p030, since the versanet global ne twork is sourced only for the north edge of the fpga fabric. figure 2-10 global network architecture table 2-2 proasic3 globals/spines/rows by device a3p030 A3P060 a3p125 a3p250 a3p400 a3p600 a3p1000 global versanets (trees)* 6 9 9 9 9 9 9 versanet spines/tree 4 4 4 8 8 12 16 total spines 24 36 36 72 72 108 144 versatiles in each top or bottom spine 384 384 384 768 768 1,152 1,536 total versatiles 768 1,536 3,072 6,144 9,216 13,824 24,576 note: *there are six chip (main) globals and three gl obals per quadrant (except in the a3p030 device). north quadrant global network south quadrant global network chip (main) global network 3 3 3 333 3 333 6 6 6 6 6 6 6 6 global spine quadrant global spine ccc ccc ccc ccc ccc ccc
proasic3 flash family fpgas advanced v0.2 2-11 bottom spine segments, radiating from the center of a device, are the same height. each spine covers a certain area of the proasic3 device (the "scope" of the spine). eac h spine is accessed by the dedicated global network mu x tree architecture, which defines how a particular spine is driven?either by the signal on the global network from a ccc, for example, or another net defined by the user ( figure 2-12 on page 2- 12 ). quadrant spines can be driven from user i/os on the north and south sides of the die. the ability to drive spines in the quadrant global networks can have a significant effect on system performance for high-fanout inputs to a design. details of the chip (main) gl obal network spine-selection mux are presented in figure 2-12 on page 2-12 . the spine drivers for each spine are located in the middle of the die. quadrant spines are driven from a north or south rib. access to the top and bottom ribs is from the corner ccc or from the i/o on the nort h and south sides of the device. for details on using spines in proasic3 devices, see the actel application note optimal usage of global network spines in proasic plus devices . figure 2-11 spines in a global clock tree network top spine bottom spine t1 b1 t2 b2 t3 b3 pad ring pad ring pad ring i/o ring i/o ring chip (main) global pads global pads high-performance global network global spine global ribs spine-selection mux tree logic tiles quadrant global pads
proasic3 flash family fpgas 2-12 advanced v0.2 clock aggregation clock aggregation allows fo r multi-spine clock domains. a mux tree provides the nece ssary flexibility to allow long lines or i/os to access do mains of one, two, or four global spines. signal access to the clock aggregation system is achieved through long-line resources in the central rib, and also through local resources in the north and south ribs, allo wing i/os to directly feed into the clock system. as figure 2-13 indicates, this access system is contiguous. there is no break in the middl e of the chip for the north and south i/o versanet access. this is different from the quadrant clocks, located in these ribs, which only reach the middle of the rib. refer to the using global resources in actel proasic3/e devices application note. figure 2-12 spine selection mu x of global tree figure 2-13 clock aggregation tree architecture internal/external signal internal/external signal internal/external signals spine global rib global driver mux tree node mux tree node mux internal/external signals tree node mux global spine global rib global driver and mux i/o access internal signal access i/o tiles global signal access tree node mux
proasic3 flash family fpgas advanced v0.2 2-13 clock conditioning circuits overview of clock conditioning circuitry in proasic3 devices, the clock conditioning circuits (cccs) are used to implement freq uency division, frequency multiplication, phase shifti ng, and delay operations. the cccs are available in six chip locations ? each of the four chip corners and in th e middle of the east and west chip sides. each ccc can implement up to three independent global buffers (with or without programmable delay), or a pll function (programmable frequency division/ multiplication, phase shift, an d delays) with up to three global outputs. unused global outputs of a pll can be used to implement independent global buffers, up to a maximum of three global outputs for a given ccc. a global buffer can be placed in any of the three global locations (clka-gla, clkb-glb, and clkc-glc) of a given ccc. a pll macro uses the clka ccc input to drive its reference clock. it uses the gla and optionally the glb and glc global outputs to drive the global networks. a pll macro can also drive the yb and yc regular core outputs. the glb (or glc) global outputs cannot be reused if the yb (or yc) outputs are used ( figure 2-14 on page 2-14 ). each global buffer, as well as the pll reference clock, can be driven from one of the following: three dedicated single-ended i/os using a hardwired connection two dedicated differential i/os using a hardwired connection the fpga core the ccc block is fully conf igurable, either via flash configuration bits set in the programming bitstream or through an asynchronous in terface. this asynchronous interface is dynamically a ccessible from inside the proasic3 device to permit parameter changes (such as divide ratios) during device operation. to increase the versatility and flexibility of the clock conditioning system, the ccc configuration is determined either by the user during the design process, with configuration data being stored in flash memory as part of the device programming procedure, or by writing data into a dedicated shift register during normal device operation. this latter mode allows the user to dynamically reconfigure the ccc without the need for core programming. the shift register is accessed through a simple serial interface. refer to the ujtag applications in proasic3/e devices application note and the "ccc electrical specificati ons" section on page 2-18 for more information. global buffers with no programmable delays the clkbuf and clkbuf_lvpecl/lvds macros are composite macros that incl ude an i/o macro driving a global buffer, which uses a hardwired connection. the clkbuf, clkbuf_lvpecl/lvds, and clkint macros are pass-through clock source s and do not use the pll or provide any programmable delay functionality. the clkint macro provides a global buffer function driven by the fpga core. many specific clkbuf macros support the wide variety of single-ended and differential i/o standards supported by proasic3 devices. the available clkbuf macros are described in the proasic3/e macro library guide . global buffer with programmable delay the clkdly macro is a pass-through clock source that does not use the pll, but prov ides the ability to delay the clock input using a programmable delay. the clkdly macro takes the selected cl ock input and adds a user- defined delay element. this has the effect of a frequency-dependent output clock phase shift from the input clock. the clkdly macro can be driven by an inbuf macro to create a composite macro, where the i/o macro drives the global buffer (with programmable delay) using a hardwired connection. in this case, the i/o must be placed in one of the dedicated global i/o locations. the clkdly macro can be driven directly from the fpga core. the clkdly macro can also be driven from an i/o that is routed through the fpga regular routing fabric. in this case, users must instantiate a special macro, pllint, to differentiate from the hardwired i/o connection described earlier. the visual clkdly configurat ion in the actgen part of the libero ide and designer tools allows the user to select the desired amount of delay, and configures the delay elements appropriately. actgen also allows the user to select where the in put clock is coming from. actgen will automatically in stantiate the special macro, pllint, when needed. many specific inbuf macros support the wide variety of single-ended and differential i/o standards supported by the proasic3 family. the available inbuf macros are described in the proasic3/e macro library guide .
proasic3 flash family fpgas 2-14 advanced v0.2 notes: 1. see the actel website for future applicat ion notes concerning the dynamic pll.the pll is only supported on the west center cc c. the a3p030 has no pll support. refer to "pll function" section on page 2-15 for signal descriptions. 2. refer to the proasic3/e macro library guide for more information. figure 2-14 proasic3 ccc options clkbuf_lvds/lvpecl macro padn padp padn padp y y y a pad y pad y clkint macro clkbuf macro input lvds/lvpecl macro pll macro inbuf* macro gla or gla and (glb or yb) or gla and (glc or yc) or gla and (glb or yb) and (glc or yc) gla or glb or glc clock source clock conditioning output oadiv[4:0] oamux[2:0] dlygla[4:0] obdiv[4:0] obmux[2:0] dlyyb[4:0] dlyglb[4:0] ocdiv[4:0] ocmux[2:0] dlyyc[4:0] dlyglc[4:0] findiv[6:0] fbdiv[6:0] fbdly[4:0] fbsel[1:0] xdlysel vcosel[2:0] clka extfb gla lock glb yb glc yc powerdown clkdly macro clk gl dlygl[4:0]
proasic3 flash family fpgas advanced v0.2 2-15 pll function 1 the pll functionality of the clock conditioning block is supported by the pll macro. note that the pll macro reference clock uses the clka input of the ccc block, which is only accessible from the global a[0:2] package pins. refer to figure 2-15 on page 2-16 for more information. the pll macro supports three inputs and up to six outputs ( figure 2-17 on page 2-17 ). inputs: clka: selected clock input extfb: allows an external signal to be compared to a reference clock in the pll core's phase detector powerdown (active low): disables plls. the default state is powerdown on (active low). outputs: lock: indicates that pll output has locked on the input reference signal gla, glb, glc: outputs to respective global networks yb, yc: allows output from the ccc to be routed back to the fpga core as previously described, the p ll allows up to five flexible and independently configurable clock outputs. figure 2-14 on page 2-14 illustrates the various clock output options and delay elements. as illustrated, the pll will su pport three di stinct output frequencies from a given input clock. two of these (glb and glc) can be routed to the b and c global network access, respectively, and/or routed to the device core (yb and yc). also in the feedback loop, there is a delay element that can be used to advance th e clock relative to the reference clock. there are five delay elements to support phase control on all five outputs (gla, glb, glc, yb, and yc). note: care must be taken if the output delay element is used in conjunction with an output divide. as there are a finite number of dividers and delay elements, exact output frequency and output phase may not always be derived from the input clock frequency. the pll macro reference clock can be driven by an inbuf macro to create a composite macro, where the i/o macro drives the global buffer (with programmable delay) using a hardwired connection. in this case, the i/o must be placed in one of the dedicated global i/o locations. the pll macro reference clock can be driven directly from the fpga core. the pll macro reference clock can also be driven from an i/o that is routed throug h the fpga regular routing fabric. in this case, users mu st instantiate a special macro, pllint, to differentiate from the hardwired i/o connection described earlier. the visual pll configuration in actgen, associated with the libero ide and designer tools, will derive the necessary internal divider ratios based on the input frequency and desired output frequencies selected by the user. actgen also allows the user to select the various delays and phase shift values necessary to adjust the phases between the refe rence clock (clka) and the derived clocks (gla, glb, glc, yb and yc). actgen also allows the user to select wh ere the input cl ock is coming from. actgen automatically instantiates the special macro, pllint, when needed. 1. the a3p030 device does not support pll.
proasic3 flash family fpgas 2-16 advanced v0.2 notes: 1. represents the global input pins. globals have direct access to the clock conditioning block and are not routed via the fpga fabric. refer to the "user i/o naming convention" on page 2-44 for more information. 2. instantiate the routed clock source input as follows: a) connect the output of a logic element to th e clock input of pll, clkdly, or clkint macro. b) do not place a clock source i/o (inbuf or in buf_lvpecl/lvds) in a relevant global pin location. 3. lvds-based clock sources are only available on a3p250 through a3p1000 family members. A3P060 and a3p125 support single- ended clock sources only. the a3p030 device does not support this feature. figure 2-15 clock input sources including clkbuf, clkbuf_lvds/lvpecl, and clkint note: the a3p030 device does not support this feature. figure 2-16 clkbuf and clkint + + source for ccc (clka or clkb or clkc) each shaded box represents an input buffer called out by the appropriate inbuf or inbuf_lvds/lvpecl. to core routed clock (from fpga core) sample pin names gaa0/io0ndb0v0 1 gaa1/io00pdb0v0 1 gaa2/io13pdb7v1 1 gaa[0:2]: ga re p resents g lobal in the northwest corner 2 clkbuf clkint clkbuf_lvds/lvpecl padn padp y pad y y a
proasic3 flash family fpgas advanced v0.2 2-17 table 2-3 available selections of i/o standards within clkbuf and clkbuf_lvds/lvpecl macros clkbuf macros clkbuf_lvcmos5 clkbuf_lvcmos33* clkbuf_lvcmos18 clkbuf_lvcmos15 clkbuf_pci clkbuf_lvds clkbuf_lvpecl note: *by default, the clkbuf macro uses the 3.3 v lvttl i/o technology. for more details refer to the proasic3/e macro library guide . note: *see the actel website for future application notes concerning the dynamic pll. the a3p030 device does not support pll. figure 2-17 ccc/pll macro clka extfb gla lock glb yb glc yc powerdown oadiv[4:0]* oamux[2:0]* dlygla[4:0]* obdiv[4:0]* obmux[2:0]* dlyyb[4:0]* dlyglb[4:0]* ocdiv[4:0]* ocmux[2:0]* dlyyc[4:0]* dlyglc[4:0]* findiv[6:0]* fbdiv[6:0]* fbdly[4:0]* fbsel[1:0]* xdlysel* vcosel[2:0]* note: the clkdly macro uses progra mmable delay element type 2. figure 2-18 clkdly clkdly clk gl dlygl[4:0]
proasic3 flash family fpgas 2-18 advanced v0.2 ccc electrical specifications timing characteristics table 2-4 proasic3 ccc/pll specification parameter min. typ. max. unit clock conditioning circuitry input frequency f in_ccc 1.5 350 mhz clock conditioning circuitry output frequency f out_ccc 0.75 350 mhz delay increments in programmable delay blocks 1, 2 160 ps number of programmable values in each programmable delay block 32 input period jitter 1.5 ns long term output pk-pk period jitter at f pll_out = 24 mhz ? 180 ps at f pll_out = 100 mhz ? 90 ps at f pll_out = 350 mhz ? 70 ps acquisition time 150 s output duty cycle 48.5 51.5 % delay range in block: programmable delay 1 1, 2 0.6 5.56 ns delay range in block: programmable delay 2 1, 2 0.025 5.56 ns delay range in block: fixed delay 1, 2 2.2 ns notes: 1. this delay is a function of voltage and temperature. see table 3-6 on page 3-4 for deratings. 2. t j = 25c, v cc = 1.5 v 3. the a3p030 device does not support pll.
proasic3 flash family fpgas advanced v0.2 2-19 physical implemen tation of ccc 2 the ccc circuit is compos ed of the following ( figure 2-19 ): pll core three phase selectors six programmable delays and one fixed delay that advance/delay phase five programmable frequency dividers that provide frequency multip lication/division (not shown in figure 2-19 , because they are automatically configured based on the user's required frequencies) one dynamic shift register that provides ccc dynamic reconfiguration capability ccc programming the clock conditioning circuit block is fully configurable, either via static flash configur ation bits in the array, set by the user in the programming bitstream, or through an asynchronous dedicated shift register dynamically accessible from inside the proasic3 device. the dedicated shift register permits parameter changes such as pll divide ratios and delays during device operation. this latter mode allows the user to dynamically reconfigure the pll without the need for core programming. the register file is accessed through a simple serial interface. refer to the ujtag applications in proasic3/e devices application note for more information. 2. the a3p030 device does not support pll. note: refer to the "clock conditioning circuits" section on page 2-13 and table 2-4 on page 2-18 for signal descriptions. figure 2-19 pll block pll core phase select phase select phase select gla clka extfb glb yb glc yc fixed delay programmable delay type 1 programmable delay type 2 programmable delay type 2 programmable delay type 1 programmable delay type 2 programmable delay type 1 clock divider and clock multiplier blocks are not shown in this figure or in actgen. they are automatically configured based on the user's required frequencies. four-phase output
proasic3 flash family fpgas 2-20 advanced v0.2 nonvolatile memory (nvm) overview of user n onvolatile flashrom (from) proasic3 devices have 1 kbit of on-chip nonvolatile flash memory that can be read from the fpga core fabric. the from is arranged in 8 banks of 128 bits during programming. the 128 bits in each bank are addressable as 16 bytes during the read ba ck of the from from the fpga core ( figure 2-20 ). the from can only be programmed via the ieee1532 jtag port. it cannot be programmed directly from the fpga core. when programmi ng, each of the 8 128-bit banks can be selectively reprogrammed. the from can only be reprogrammed on a bank boundary. programming involves an automatic, on-chip bank erase prior to reprogramming the bank. the from supports asynchronous read with a no minal 10 ns access time. the from can be read on byte boundaries. the top 3 bits of the from address from the fpga core define the bank that is being accessed. the bottom 4 bits of the from address from the fpga core define which of the 16 bytes in the bank is being accessed. figure 2-20 from architecture bank number 3 msb of addr (read) byte number in bank 4 lsb of addr (read) 0 7 6 5 4 3 2 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
proasic3 flash family fpgas advanced v0.2 2-21 sram and fifo 3 proasic3 devices have embedded sram blocks along the north side of the device. in addition, a3p600 and a3p100 have an embedded sram block on the south side of the device. to meet the needs of high performance designs, the memory blocks operate strictly in synchronous mode for both read and write opera tions. the read and write clocks are completely independent, and each may operate at any desired frequency less than or equal to 350 mhz. 4kx1, 2kx2, 1kx4, 512x9 (dual-port ram ? two read, two write or one read, one write) 512x9, 256x18 (two-port ra m ? one read and one write) sync write, sync pipelined, and nonpipelined read the proasic3 memory block includes dedicated fifo control logic to generate internal addresses and external flag logic (full, empty, afull, aempty). block diagrams of the memory modules are illustrated in figure 2-21 on page 2-22 . during ram operation, addr esses are sourced by the user logic and the fifo controller is ignored. in fifo mode, the internal addresses are generated by the fifo controller and routed to the ram array by internal muxes. refer to figure 2-22 on page 2-23 for more information about the implementation of the embedded fifo controller. the proasic3 architecture enables the read side and write side of rams to be organized independently, allowing for bus conversion. for example, the write side can be set to 256x18 and the read side to 512x9. both the write width and read width for the ram blocks can be specified independently with the ww (write width) and rw (read width) pins. the different dxw configurations are: 256x18, 512x9, 1kx4, 2kx2, and 4kx1. refer to the allowable rw and ww values supported for each of the ram macro types in table 2-5 on page 2-24 . when widths of one, two, and four are selected, the ninth bit is unused. for example, when writing nine-bit values and reading four-bit values, only the first four bits and the second four bits of each nine-bit value are addressable for read operat ions. the ninth bit is not accessible. conversely, when writing fo ur-bit values and reading nine-bit values, the ninth bi t of a read operation will be undefined. the ram blocks employ little-endian byte order for read and write operations. 3. the a3p030 device does not support sram and fifo.
proasic3 flash family fpgas 2-22 advanced v0.2 note: the a3p030 device does not support sram and fifo. figure 2-21 supported basic ram macros fifo4k18 rw2 rd17 rw1 rd16 rw0 ww2 ww1 ww0 rd0 estop fstop full afull empty afval11 aempty afval10 afval0 aeval11 aeval10 aeval0 ren rblk rclk wen wblk wclk rpipe wd17 wd16 wd0 reset addra11 douta8 douta7 douta0 doutb8 doutb7 doutb0 addra10 addra0 dina8 dina7 dina0 widtha1 widtha0 pipea wmodea blka wena clka addrb11 addrb10 addrb0 dinb8 dinb7 dinb0 widthb1 widthb0 pipeb wmodeb blkb wenb clkb ram4k9 raddr8 rd17 raddr7 rd16 raddr0 rd0 wd17 wd16 wd0 ww1 ww0 rw1 rw0 pipe ren rclk ram512x18 waddr8 waddr7 waddr0 wen wclk reset reset
proasic3 flash family fpgas advanced v0.2 2-23 note: the a3p030 device does not support sram and fifo. figure 2-22 proasic3 ram block with embedded fifo controller cnt 16 e = e = afval aeval v v= sub 16 cnt 16 rclk wd wclk reset wblk wen fstop rblk ren estop rd [17:0] wd [17:0] rclk wclk radd [j:0] wadd [j:0] ren fren fwen wen full aempty afull empty rd rpipe rw[2:0] ww[2:0] ram
proasic3 flash family fpgas 2-24 advanced v0.2 signal descript ions for ram4k9 4 the following signals are us ed to configure the ram4k9 memory element: widtha and widthb these signals enable the ram to be configured in one of four allowable aspect ratios ( table 2-5 ). blka and blkb these signals are active low and will enable the respective ports when assert ed. when a blkx signal is deasserted, that port?s outp uts hold the previous value. wena and wenb these signals switch the ra m between read and write modes for the respective ports. a low on these signals indicates a write operation, and a high indicates a read. clka and clkb these are the clock signals fo r the synchronous read and write operations. these can be driven independently or with the same driver. pipea and pipeb these signals are used to sp ecify pipelined read on the output. a low on pipea and/or pipeb indicates a nonpipelined read and th e data appears on the corresponding output in the same clock cycle. a high indicates a pipelined read and data appears on the corresponding output in the next clock cycle. wmodea and wmodeb these signals are used to co nfigure the behavior of the output when ram is in the write mode. a low on these signals makes the output reta in data from the previous read. a high indicates pass-through behavior where the data being written will appear immediately on the output. this signal gets overridden when ram is being read. reset this active low signal resets the output to zero when asserted. it does not reset the content of the memory. addra and addrb these are used as read or write addresses and are 12 bits wide. when a depth of less than 4 k is specified, the unused high-order bits must be grounded ( table 2-6 ). dina and dinb these are the input data signa ls, and these are nine bits wide. not all nine bits are valid in all configurations. when a data width less than nine is specified, unused high-order signals must be grounded ( table 2-7 ). douta and doutb these are the output data si gnals, and these are nine bits wide. not all nine bits are valid in all configurations. as with dina and dinb, high-order bits become unusable. the output data on unused pins is undefined. signal descripti ons for ram512x18 4 ram512x18 has slightly different behavior than the ram4k9, as it has dedicated read and write ports. ww and rw these signals enable the ram to be configured in one of the two allowable aspect ratios ( table 2-8 ). 4. the a3p030 device does not support sram and fifo. table 2-5 allowable aspect ratio settings for widtha[1:0] widtha1, widtha0 widthb1, widthb0 dxw 00 00 4kx1 01 01 2kx2 10 10 1kx4 11 11 512x9 table 2-6 address pins used for various supported bus widths dxw addra/addrb unused 4kx1 ? 2kx2 addra[11], addrb[11] 1kx4 addra[11: 10], addrb[11:10] 512x9 addra[11:9] , addrb[11:9] table 2-7 data pins used for various supported bus widths dxw dina/dinb unused 4kx1 dina[8:1], dinb[8:1] 2kx2 dina[8:2], dinb[8:2] 1kx4 dina[8:4], dinb[8:4] 512x9 ? table 2-8 aspect ratio settings for ww[1:0] ww1, ww0 rw1, rw0 dxw 01 01 512x9 10 10 256x18 00, 11 00, 11 reserved
proasic3 flash family fpgas advanced v0.2 2-25 wd and rd these are the input data an d output signals, and they are 18 bits wide. when a 512x9 aspect ratio is used for write, wd[17:9] are unused and must be grounded. if this aspect ratio is used for read, then rd[17:9] are undefined. waddr and raddr these are read and write ad dresses, and they are nine bits wide. when the 256x18 as pect ratio is used for write or read, waddr[8] or raddr[ 8] is unused and must be grounded. wclk and rclk these signals are the write a nd read clocks, respectively. they are both active high. wen and ren these signals are the write and read enables, respectively. they are both active low by default. these signals can be configured as active high. reset this active low signal resets the output to zero when asserted. it does not reset the contents of the memory. pipe this signal is used to sp ecify pipelined read on the output. a low on pipe indicates a nonpipelined read and the data appears on the output in the same clock cycle. a high indicates a pipelined r ead and data appears on the output in the next clock cycle. clocking the dual-port sram blocks are only clocked on the rising edge. actgen allows falling- edge triggered clocks by adding inverters to the netlis t, hence achieving dual-port sram blocks that are clocke d on either edge (rising or falling). for dual-port sram, each port can be clocked on either edge and/or by separate clocks by port. proasic3 devices support inversion (bubble pushing) throughout the fpga architecture, including the clock input to the sram modules. inversions added to the sram clock pin on the design schematic or in the hdl code will be automatically accounted for during design compile without incurring additional delay in the clock path. the two-port sram can be clocked on the rising edge or falling edge of the wclk and rclk. if negative-edge ram and fifo clocking is selected for memory macros, clock edge inversion management (bubble pushing) is automatically used within the proasic3 development tools, without performance penalty. modes of operation there are two read mode s and one write mode: read nonpipelined (synchronous ? one clock edge): in the standard read mode, new data is driven onto the rd bus in the clock cycle immediately following ra and ren valid. the read address is registered on the read port clock active edge and data appears at rd after the ram access time. setting pipe to off enables this mode. read pipelined (synchro nous ? two clock edges): the pipelined mode incurs an additional clock delay from the address to the data but enables operation at a much high er frequency. the read address is registered on th e read port active clock edge, and the read data is registered and appears at rd after the second read clock edge. setting the pipe to on enables this mode. write (synchronous ? one clock edge): on the write clock active edge, the write data is written into the sram at the wr ite address when wen is high. the setup times of the write address, write enables, and write data are minimal with respect to the write clock. writ e and read transfers are described with timing requirements in the "ddr module specifications" section on page 3-37 . ram initialization each sram block can be individually initialized on power-up by means of the jtag port using the ujtag mechanism (refer to the "jtag 1532" section on page 2- 48 and the proasic3/e sram/fifo blocks application note). the shift register for a target block can be selected and loaded with the proper bit configuration to enable serial loading. the 4,608 bits of data can be loaded in a single operation. signal descripti ons for fifo4k18 5 the following signals are used to configure the fifo4k18 memory element: ww and rw these signals enable the fifo to be configured in one of the five allowable aspect ratios ( table 2-9 ). 5. the a3p030 device does not support sram and fifo. table 2-9 aspect ratio settings for ww[2:0] ww2, ww1, ww0 rw2, rw1, rw0 dxw 000 000 4kx1 001 001 2kx2 010 010 1kx4 011 011 512x9 100 100 256x18 101, 110, 111 101, 110, 111 reserved
proasic3 flash family fpgas 2-26 advanced v0.2 wblk and rblk these signals are active low and will enable the respective ports when low. when the rblk signal is high, that port?s outputs hold the previous value. wen and ren read and write enables. wen is active low and ren is active high by default. these signals can be configured as active high or low. wclk and rclk these are the clock signals fo r the synchronous read and write operations. these can be driven independently or with the same driver. rpipe this signal is used to sp ecify pipelined read on the output. a low on rpipe indicates a nonpipelined read and the data appears on the output in the same clock cycle. a high indicates a pipe lined read and data appears on the output in the next clock cycle. reset this active low signal resets the output to zero when asserted. it resets the fifo counters. it also sets all the rd pins low, the full and afull pins low, and the empty and aempty pins high ( table 2-10 ). wd this is the input data bus an d is 18 bits wide. not all 18 bits are valid in all config urations. when a data width less than 18 is specified, unused higher-order signals must be grounded ( table 2-10 ). rd this is the output data bus and is 18 bits wide. not all 18 bits are valid in all configur ations. like the wd bus, high- order bits become unusable if the data width is less than 18. the output data on unused pins is undefined ( table 2-10 ). estop, fstop estop is used to stop the fi fo read counter from further counting once the fifo is empty (i.e., the empty flag goes high). a high on this signal inhibits the counting. fstop is used to stop the fifo write counter from further counting once the fifo is full (i.e., the full flag goes high). a high on this sign al inhibits the counting. for more information on these signals, refer to the "estop and fstop usage" section . full, empty when the fifo is full and no more data can be written, the full flag asserts high. the full flag is synchronous to wclk to inhibit writing immediately upon detection of a full condition and to prevent overflows. since the write address is compared to a resy nchronized (and thus time- delayed) version of the read address, the full flag will remain asserted until two wclk active edges after a read operation eliminates the full condition. when the fifo is empty and no more data can be read, the empty flag asserts high. the empty flag is synchronous to rclk to inhibit reading immediately upon detection of an empty condition and to prevent underflows. since the read address is compared to a resynchronized (and thus time delayed) version of the write address, the empty fl ag will remain asserted until two rclk active edges, after a write operation, removes the empty condition. for more information on these signals, refer to the "fifo flags usage considerations" section on page 2-27 . afull, aempty these are programmable flag s and will be asserted on the threshold specified by afval and aeval, respectively. when the number of words st ored in the fifo reaches the amount specified by aeval while reading, the aempty output will go high. likewise, when the number of words stored in the fifo reaches the amount specified by afval while writing, the afull output will go high. afval, aeval the aeval and afval pins are used to specify the almost-empty and almost-full threshold values, respectively. they are 12-bit signals. for more information on these signals, refer to the "fifo flags usage considerations" section on page 2-27 . estop and fstop usage the estop pin is used to stop the read counter from counting any further once the fifo is empty (i.e., the empty flag goes high). likewis e, the fstop pin is used to stop the write counter from counting any further once the fifo is full (i.e., the full flag goes high). the fifo counters in the pr oasic3 device start the count from 0, reach the maximum depth for the configuration (e.g., 511 for a 512x9 configur ation), and then restart from 0. an example applicat ion for the esto p, where the read counter keeps counting, would be writing to the fifo once and reading the same content over and over, without doing a write again. table 2-10 input data signal usage for different aspect ratios dxw wd/rd unused 4kx1 wd[17:1], rd[17:1] 2kx2 wd[17:2], rd[17:2] 1kx4 wd[17:4], rd[17:4] 512x9 wd[17:9], rd[17:9] 256x18 ?
proasic3 flash family fpgas advanced v0.2 2-27 fifo flags usage considerations the aeval and afval pins are used to specify the almost-empty and almost-full threshold values, respectively. they are 12-bit signals. in order to handle different read and write aspect ratios, the values specified by the aeval and afval pins are to be interpreted as the address of the last word stored in the fifo. the fifo actually cont ains separate write address (waddr) and read address (raddr) counters. these counters calculate the 12-bit memory address that is a function of ww and rw, respectively. waddr is incremented every time a wr ite operation is performed, and raddr is incremented ever y time a read operation is performed. whenever the difference between waddr and raddr is greater than or equal to afval, the afull output is asserted. likewis e, whenever the difference between waddr and raddr is less than or equal to aeval, the aempty output is asserted. to handle different read and write aspect ratios, the afval and aeval are expressed in terms of total data bits instead of total data words. when users specify the afval and aeval in terms of read or write words, the actgen tool translates th em into bit addresses and configures these signals. actgen configures the almost -full flag, afull, to assert when the write address exc eeds the read address by a predefined value. assume the user has a 2kx8 fifo, a value of 1,500 for afval means that the afull flag will be asserted when a write ca uses the difference between the write address and the read address to be 1,500. the aempty flag is asserted when the difference between the write address and the read address is less than a predefined value. in the ex ample above, a value of 200 for aeval means that the aempty flag will be asserted when a read causes the di fference between the write address and the read address to drop to 200. note that the fifo can be configured wi th different read and write widths; in this case the afval setting is based on the number of write data entries and the aeval setting is based on the number of read data entries. in the case of 512x9 and 256x18 aspect ratios, since only 4,096 bits can be addressed by 12 bits of the afval/ aeval, the number of words must be multiplied by 8 and 16, instead of 9 an d 18. the actgen tool automatically uses the proper values. to avoid half words being written or read, which could happen if different read and write aspect ratios are specified, the fifo will assert full or empty as soon as at least a minimum of one word cannot be written or read. for example, if a two-bit wo rd is written and a four-bit word is being read, fifo wi ll remain in the empty state when the first word is writte n. this occurs even if the fifo is not completely empty, because at this time a single word cannot be read. th e same is applicable in the full state. if a four-bit word is written and a two-bit word is read, the fifo is full an d one word is read. the full flag will remain asserted because a complete word cannot be written at this point. refer to the proasic3/e sram/fifo blocks application note for more information. advanced i/os introduction proasic3 devices feature a flexible i/o structure, supporting a range of mixed-vo ltages (1.5 v, 1.8 v, 2.5 v, and 3.3 v) through a bank-selectable voltage. table 2-11 , table 2-12 , and table 2-18 on page 2-42 show the voltages and the compatible i/o standards. i/os provide programmable slew rates, drive strengths, weak pull-up, and weak pull-down circuits. 3.3 v pci and 3.3 v pci-x are 5 v tolerant. see the "5 v input tolerance" section on page 2-35 for possible implementations of 5 v tolerance. all i/os are in a known stat e during power-up, and any power-up sequence is allowed without current impact. refer to the "i/o power-up and supply voltage thresholds for power-on reset (commercial and industrial)" section on page 3-3 for more information. i/o tile the proasic3 i/o tile provides a flexible, programmable structure for implementing a large number of i/o standards. in addition, the registers available in selected i/o banks can be used to support high -performance register inputs and outputs, with register enable if desired ( figure 2-23 on page 2-30 ). the registers can also be used to support the jesd-79c double data rate (ddr) standard within the i/o structure (see the "double data rate (ddr) support" section on page 2-31 for more information). as depicted from figure 2-23 on page 2-30 , all i/o registers share one clr port . the output register and output enable register share one clk port. refer to the "i/o registers" section on page 2-30 for more information.
proasic3 flash family fpgas 2-28 advanced v0.2 i/o banks and i/o st andards compatibility i/os are grouped into i/o volt age banks. there are four i/o banks on the a3p250 through a3p1000. the a3p030, A3P060, and a3p125 have two i/o banks. each i/o voltage bank has dedicated input/output supply and ground voltages (vmv/gndq for input buffers and v cci / gnd for output buffers). because of these dedicated supplies, only i/os with co mpatible standards can be assigned to the same i/o voltage bank. table 2-12 shows the required voltage compatibility values for each of these voltages. for more information about i/o and global assignments to i/o banks, refer to the specific pin table of the device in the "package pin assignments" section on page 4-1 and the "user i/o naming convention" section on page 2-44 . i/o standards are comp atible if their v cci and vmv values are identical. vmv and gndq are "quiet" input power supply pins and are not used on a3p030. table 2-11 proasic3 supported i/o standards a3p030 A3P060 a3p125 a3p250 a3p400 a3p600 a3p1000 single-ended lvttl/lvcmos 3.3 v, lvcmos 2.5 v / 1.8 v / 1.5v, lvcmos 2.5/5.0v ??????? 3.3 v pci / 3.3 v pci-x ? ?????? differential lvpecl and lvds ? ? ? ???? table 2-12 v cci voltages and comp atible standards v cci and vmv (typ.) compatible standards 3.3 v lvttl/lvcmos 3.3, pci 3.3, lvpecl 2.5 v lvcmos 2.5, lvcmos 2.5/5.0, lvds 1.8 v lvcmos 1.8 1.5 v lvcmos 1.5
proasic3 flash family fpgas advanced v0.2 2-29 features supported on every i/o table 2-13 lists all features suppo rted by transmitter/receiver for single-ended and differential i/os. table 2-13 i/o features feature description single-ended transmitter features hot insertion in every mode except pci or 5-v-input-tolerant (these modes use clamp diodes and do not allow hot insertion) (a3p030 only) activation of hot insertion (disabling the clamp diode) is selectable by i/os (a3p030 only) weak pull-up and pull-down two slew rates skew between output buffer enable/d isable time: 2 ns delay (delay on rising edge) and 0 ns delay on falling edge (see "selectable skew between output buffer enable /disable time" on page 2-39 for more information) three drive strengths 5 v tolerant receiver ( "5 v input tolerance" section on page 2- 35 ) lvttl/lvcmos 3.3 v outputs compatible with 5 v ttl inputs ( "5 v output tolerance" section on page 2-38 ) high performance ( table 2-14 ) single-ended receiver features elec tro-statics discharge (esd) protection high performance ( table 2-14 ) separate ground and power planes, gndq/vmv, for input buffers only to avoid output-induced noise in the input circuitry differential receiver features (a3p 250 through a3p1000) esd protection high performance ( table 2-14 ) separate ground and power plane, gndq, and vmv pins for input buffers only to avoid output-induced noise in the input circuitry cmos-style lvds or lvpecl transmitter two i/os and ex ternal resistors are used to provide a cmos-style lvds or lvpecl transmitter solution. weak pull-up and pull-down fast slew rate lvds/lvpecl differential receiver features esd protection high performance ( table 2-14 ) separate input buffer ground and power planes to avoid output- induced noise in the input circuitry table 2-14 maximum i/o frequency for single-end ed and differential i/os (maximum drive strength and high slew selected) specification performance up to lvttl/lvcmos 3.3 v 200 mhz lvcmos 2.5 v 250 mhz lvcmos 1.8 v 200 mhz lvcmos 1.5 v 130 mhz pci 200 mhz pci-x 200 mhz lvds 350 mhz lvpecl 350 mhz
proasic3 flash family fpgas 2-30 advanced v0.2 i/o registers each i/o module contains seve ral input, output, and enable registers. refer to figure 2-23 for a simplified representation of the i/o block. the number of input registers is selected by a set of switches (not shown in figure 2-23 ) in between registers to implement single or differential data transmission to and from the fpga core. the designer software sets these switches for the user. a common clr/pre signal is employed by all i/o registers wh en i/o register combining is used. input register 2 does not have a clr/pre pin, as this regi ster is used for ddr implementation. note: proasic3 i/os have registers to support ddr functionality (see the "double data rate (ddr) support" section on page 2-31 ). figure 2-23 i/o block logical representation input reg e= enable pin a io/oe io/d 0 io/iclk io/q1 io/q0 y pad 1 2 3 4 5 6 oce oce ice ice io/clr or io/pre/oce input reg input reg clr/pre clr/pre clr/pre clr/pre clr/pre clr/pre pull-up/down resistor control signal drive strength and slew-rate control output reg output reg io/d1/ice io/oclk to fpga core from fpga core output enable reg
proasic3 flash family fpgas advanced v0.2 2-31 double data rate (ddr) support proasic3 devices suppor t 350 mhz ddr inputs and outputs. in ddr mode, new data is present on every transition of the clock signal. clock and data lines have identical bandwidth and sign al integrity requirements, making it very efficient for implementing very high- speed systems. in addition, high-speed ddr interfaces can be implemented using lvds. input support for ddr the basic structure to support a ddr input is shown in figure 2-24 . three input registers are used to capture incoming data, which is pres ented to the core on each rising edge of the i/o register clock. each i/o tile on proasic3 de vices supports ddr inputs. output support for ddr the basic ddr output structure is shown in figure 2-25 on page 2-32 . new data is presented to the output every half clock cycle. note: ddr macros and i/o registers do not require additional routing. the combiner automatically recognizes the ddr macro and pushes its registers to the i/o register ar ea at the edge of the chip. the routing delay from the i/o registers to the i/o buffers is already taken into ac count in the ddr macro. refer to the actel application note, using ddr for proasic3/e devices for more information. figure 2-24 ddr input register support in proasic3 devices input ddr data clk clkbuf inbuf out_qf (to core) ff2 ff1 inbuf clr ddr_in x x x x x x e a b c d out_qr (to core)
proasic3 flash family fpgas 2-32 advanced v0.2 figure 2-25 ddr output support for proasic3 devices data_f (from core) clk clkbuf out ff2 inbuf clr ddr_out ff1 0 1 x x x x x x x x a b d e c c b outbuf data_r (from core)
proasic3 flash family fpgas advanced v0.2 2-33 hot-swap support hot swapping (also called hot plugging) is the operation of hot insertion or hot removal of a card in (or from) a powered-up system. the levels of hot-swap support and examples of related applications are described in table 2- 15 . the i/os also need to be configured in hot insertion mode if hot plugging comp liance is required. the only proasic3 device supporti ng hot-swap is the a3p030, which supports hot-swapping when the clamp diode is disabled. for boards and cards with three levels of staging, it is assumed that card power supplies have time to reach their final value before the i/os are connected. pay attention to the sizing of power supply decoupling capacitors on the card to ensure that the power supplies are not overloaded with capacitance. cards with three levels of staging should have the following sequence: grounds powers i/os and other pins table 2-15 levels of hot-swap support hot swapping level description power applied to device bus state card ground connection device circuitry connected to bus pins example of application with cards that contain proasic3 devices compliance of proasic3 devices 1 cold swap no ? ? ? system and card is powered down, and then the card gets plugged into the system. then, the power supplies are turned on. compliant 2hot swap while reset yes held in reset state must be made and maintained for 1 ms before, during, and after insertion/ removal ? in pci hot-plug specification, reset control circuitry isolates the card busses until the card supplies are at their nominal operating levels and stable. compliant 3hot swap while bus idle yes held idle (no ongoing i/o processes during insertion/removal same as level 2 must remain glitch-free during power up or power down board bus shared with card bus is "frozen", and there is no toggling activity on the bus, and it is critical that the logic states set on the bus signal do not get disturbed during card insertion/removal. compliant with cards with three levels of staging 4hot swap on an active bus yes bus may have active i/o processes ongoing, but device being inserted or removed must be idle same as level 2 same as level 3 there is activity on the system bus, and it is critical that the logic states set on the bus signal do not get disturbed during card insertion/removal. compliant with cards with three levels of staging
proasic3 flash family fpgas 2-34 advanced v0.2 electro-static discharge (esd) protection proasic3 devices are tested per jedec standard jesd22-a114-b. proasic3 devices contain clamp diodes at every i/o, global, and power pad. clamp diodes protect all device pads against damage from es d as well as from excessive voltage transients. each i/o has two clamp diodes. one diode has its positive (p) side connected to pad, and its negative (n) side connected to v cci . the second diode has its p side connected to gnd, and its n side connected to pad. during operation, these diodes are normally biased in the off state, except when transient voltage is significantly above v cci or below gnd levels. in a3p030, the first diode is always off while on other proasic3 devices, the clamp diode is always on and cannot be switched off. by selecting the appropriate i/o configuratio n, the diode is turned on or off. refer to table 2-16 for more information about the i/o standards and the clamp diode. the second diode is always connected to the pad, regardless of the i/o configuration selected. table 2-16 proasic3i/o hot-swap and 5 v input tolerance capabilities i/o assignment clamp diode 1 hot insertion 5 v input tolerance 2 input buffer output buffer a3p030 other proasic3 devices a3p030 other proasic3 devices a3p030 other proasic3 devices 3.3 v lvttl/lvcmos no yes yes no yes 2 yes 2 enabled/disabled 3.3 v pci, 3.3 v pci-x n/a yes n/a no n/a yes 2 enabled/disabled lvcmos 2.5 v 3 no yes yes no yes 2 yes 3 enabled/disabled lvcmos 2.5 v / 5.0 v 3 no yes yes no yes 2 yes 3 enabled/disabled lvcmos 1.8 v no yes yes no no no enabled/disabled lvcmos 1.5 v no yes yes no no no enabled/disabled differential, lvds/ lvpecl 4 n/a yes n/a no n/a no enabled/disabled notes: 1. the clamp diode is always off for the a3p030 devi ce and always active for other proasic3 devices. 2. can be implemented with an external idt bus sw itch, resistor divider, or zener with resistor. 3. can be implemented with an external resistor and an internal clamp diode. 4. lvcmos 2.5 v and lvcmos 2.5 v / 5.0 v i/o standards are id entical in the proasic3 family. for the a3p030 device, these standards have no clamp diode; therefore, they both behave like a lvcmos 2.5 v st andard. for other proasic3 devices, these standards have a clamp diode; therefore, they both behave like lvcmos 2.5 v / 5.0 v input standard. 5. bidirectional lvds or lvpecl buffers are not supported. i/os can either be configured as input buffers or output buffers.
proasic3 flash family fpgas advanced v0.2 2-35 5 v input tolerance i/os can support 5 v input tolerance when lvttl 3.3 v, lvcmos 3.3 v, lvcmos 2.5 v and lvcmos 2.5 v configurations are used (see table 2-17 on page 2-38 for more details). there are f our recommended solutions (see figure 2-26 to figure 2-29 on page 2-38 for details of board and macro setups) to achieve 5 v receiver tolerance. all the solutions meet a common requirement of limiting the voltage at the i/o input to 3.6 v or less. in fact, the i/o absolute maximum voltage rating is 3.6 v, and any voltage above 3.6 v may cause long term gate oxide failures. solution 1 the board-level needs to ensure that the reflected waveform at the pad does no t exceed limits provided in table 3-3 on page 3-2 . this is a long term reliability requirement. this scheme will also work for a 3.3 v pci / pci-x configuration, but the internal diode should not be used for clamping, and the voltage mu st be limited by the two external resistors as explained below. relying on the diode clamping would create an excessive pad dc voltage of 3.3 v + 0.7 v = 4 v. examples of possible resi stor values (based on a simplified simulation model with no line effects, and 10 ? transmitter output resistance, where rtx_out_high = (v cci - v oh )/ i oh , rtx_out_low = v ol / i ol ). example 1: (high speed, high current) rtx_out_high = rtx_out_low = 10 ? r1 = 36 ? (+/-5%), p(r1)min = 0.069 ? r2 = 82 ? (+/-5%), p(r2)min = 0.158 ? imax_tx = 5.5 v / (82 * 0.95 + 36 * 0.95 +10) = 45.04 ma t rise = t fall = 0.85 ns at c_pad_load = 10 pf (includes up to 25% safety margin) t rise = t fall = 4 ns at c_pad_load = 50 pf (includes up to 25% safety margin) example 2: (low-medium speed, medium current) rtx_out_high = rtx_out_low = 10 ? r1 = 220 ? (+/-5%), p(r1)min = 0.018 ? r2 = 390 ? (+/-5%), p(r2)min = 0.032 ? imax_tx = 5.5 v / (220 * 0.95 + 390 * 0.95 +10) = 9.17 ma t rise = t fall = 4 ns at c_pad_load = 10 pf (includes up to 25% safety margin) t rise = t fall = 20 ns at c_pad_load = 50 pf (includes up to 25% safety margin) other values of resistors are also allowed as long as the resistors are sized appropriat ely to limit the voltage at the receiving end to 2.5 v < vin(rx) < 3.6 v* when the transmitter sends a logic '1'. this range of vin_dc(rx) has to be ensured for any combination of transmitter supply (5 v +/- 0.5 v), transmitter output resistance, and board resistor tolerances. temporary overshoots ar e allowed according to table 3-3 on page 3-2 . figure 2-26 solution 1 solution 1 5.5 v 3.3 v requires two board resistors, lvcmos 3.3 v i/os. proasic3 i/o input rext1 rext2
proasic3 flash family fpgas 2-36 advanced v0.2 solution 2 the board-level design needs to ensure that the reflected waveform at the pa d does not exceed limits provided in table 3-3 on page 3-2 . this is a long-term reliability requirement. this scheme will also work for a 3.3 v pci/pcix configuration, but the internal diode should not be used for clamping, and the voltage must be limited by the ex ternal resistors and zener, as shown in figure 2-27 . relying on the diode clamping would create an excessive pad dc voltage of 3.3 v + 0.7 v = 4 v. figure 2-27 solution 2 solution 2 5.5 v 3.3 v requires one board resistor, one zener 3.3 v diode, lvcmos 3.3 v i/os. proasic3 i/o input rext1 zener 3.3 v
proasic3 flash family fpgas advanced v0.2 2-37 solution 3 the board-level design needs to ensure that the reflected waveform at the pa d does not exceed limits provided in table 3-3 on page 3-2 . this is a long-term reliability requirement. this scheme will also work for 3.3 v pc i/pcix configuration, but the internal diode should not be used for clamping, and the voltage must be limited by the bus switch, as shown in figure 2-28 . relying on the diode clamping would create an excessive pad dc voltage of 3.3 v + 0.7 v = 4 v. figure 2-28 solution 3 solution 3 requires a bus switch on the board, lvttl/lvcmos 3.3 v i/os. proasic3 i/o input 3.3 v 5.5 v 5.5 v bus switch idtqs32x23
proasic3 flash family fpgas 2-38 advanced v0.2 solution 4 5 v output tolerance proasic3 i/os must be set to 3.3 v lvttl or 3.3 v lvcmos mode to reliably drive 5 v ttl re ceivers. it is also critical that there be no external i/o pull-up resistor to 5 v, since this resistor would pull th e i/o pad voltage beyond the 3.6 v absolute maximum value, and consequently cause damage to the i/o. when set to 3.3 v lvttl or 3.3 v lvcmos mode, proasic3 i/os can directly drive signals into 5 v ttl receivers. in fact, v ol = 0.4 v and v oh = 2.4 v voltages on both 3.3 v lvttl and 3.3 v lvcmos modes exceed the v il =0.8 v and v ih = 2 v level requirements of 5 v ttl receivers. therefore, level '1' and level '0' will be recognized correctly by 5 v ttl receivers. figure 2-29 solution 4 table 2-17 comparison table for 5 v compliant receiver scheme solution board components speed current limitations 1 two resistors low to high 1 limited by transmitter's drive strength 2 resistor and zener 3.3 v medium limit ed by transmitter's drive strength 3 bus switch high n/a 4 resistor 2 r = 250 ? at t j =70c r = 500 ? at t j =85c r = 1000 ? at t j = 100c low diode current 12 ma at t j =70c 6 ma at t j =85c 3 ma at t j =100c notes: 1. speed and current consumption increase as the board resistance values decrease. 2. resistor values ensure i/o diode long term reliability. solution 4 2.5 v 5.5 v on-chip clamp diode 2.5 v requires one board resistor. available for all i/o standards excluding 3.3 v i/o standards. (not supported for a3p030 device.) proasic3 i/o input rext
proasic3 flash family fpgas advanced v0.2 2-39 selectable skew between output buffer enable/disable time the configurable skew block is used to delay the output buffer assertion (enable) without affecting deassertion (disable) time. figure 2-30 block diagram of output enable path figure 2-31 timing diagram (option1: bypasses skew circuit) figure 2-32 timing diagram (opt ion 2: with skew circuit selected) enable (out) skew circuit output enable (from fpga core) i/o output buffers enable (in) mux skew select enable (in) enable (out) less than 0.1 ns less than 0.1 ns enable (in) enable (out) 1.2 ns (typ) less than 0.1 ns
proasic3 flash family fpgas 2-40 advanced v0.2 on a system level, the skew circuit can be used in applications where tran smission activities on bidirectional data lines need to be coordinated. this circuit, when selected, provides a timing margin that can prevent bus contention and subsequent data loss and/or transmitter over-stress due to transmitter-to-transmitter current shorts. figure 2-33 presents an example of the skew circuit implementation in a bidirectional communication system. figure 2-34 shows how a bus contention is created, and figure 2-35 on page 2-41 shows how it can be avoided with the skew circuit. figure 2-33 example of implementation of skew circuits in bidi rectional transmission syst ems using proasic3 devices figure 2-34 timing diagram (bypasses skew circuit) transmitter 1: proasic3 i/o transmitter 2: generic i/o enable(t2) en(b1) en(b2) routing delay (t1) routing delay (t2) en(r1) enable(t1) skew or bypass skew bidirectional data bus transmitter enable/ disable en (b1) en (b2) enable (r1) transmitter 1: on enable (t2) transmitter 2: on enable (t1) bus contention transmitter 1: off transmitter 1: off transmitter 2: off
proasic3 flash family fpgas advanced v0.2 2-41 figure 2-35 timing diagram (with skew circuit selected) en (b1) en (b2) transmitter 1: on enable (t2) transmitter 2: on transmitter 2: off enable (t1) result: no bus contention transmitter 1: off transmitter 1: off
proasic3 flash family fpgas 2-42 advanced v0.2 i/o software support in the proasic3 development software, default settings have been defined for the various i/o standards that are supported. changes can be made to the default settings via the use of attributes; however, not all i/o attributes are applicable for all i/o standards. table 2-18 lists the valid i/o attributes that can be manipulated by the user for each i/o standard. single-ended i/o standards in proasic3 support up to five different drive strengths. table 2-19 lists the default values for the above selectable i/o attributes as well as those that are preset for that i/o standard. see table 2-21 on page 2-43 for slew and out_drive settings. table 2-18 i/o attributes vs. i/o standard applications i/o standards slew (output only) out_drive (output only) skew (all macros with oe) res_pull out_load (output only) combine_register lvttl/lvcmos 3.3 v ????? ? lvcmos 2.5 v ????? ? lvcmos 2.5/5.0 v ????? ? lvcmos 1.8 v ????? ? lvcmos 1.5 v ????? ? pci (3.3 v) ?? pci-x (3.3 v) ?? ? lvds ?? lvpecl ?? table 2-19 i/o default attributes i/o standards slew (output only) out_drive (output only) skew) (tribuf and bibuf only) res_pull out_load (output only) combine_register lvttl/lvcmos 3.3 v see table 2-21 on page 2-43 see table 2-21 on page 2-43 off none 35 pf ? lvcmos 2.5 v off none 35 pf ? lvcmos 2.5/5.0 v off none 35 pf ? lvcmos 1.8 v off none 35 pf ? lvcmos 1.5 v off none 35 pf ? pci (3.3 v) off none 10 pf ? pci-x (3.3 v) off none 10 pf ? lvds off none 0 pf ? lvpecl off none 0 pf ?
proasic3 flash family fpgas advanced v0.2 2-43 weak pull-up and weak pull-down resistors proasic3 devices support optional weak pull-up and pull-down resistors per i/o pin. when the i/o is pulled up, it is connected to the v cci of its corresponding i/o bank. when it is pulled- down it is connected to gnd. refer to table 3-20 on page 3-16 for more information. slew rate control and drive strength proasic3 devices support output slew rate control: high and low. the a3p030 device does not suppor t slew rate control. the high slew rate option is recommended to minimize the propagation delay. this high-speed option may introduce noise into the system if appropriate signal integrity measures are not a dopted. selecting a low slew rate reduces this kind of noise but adds some delays in the system. a low slew rate is recommended when bus transients are expected. driv e strength should also be selected according to the design requirements and noise immunity of the system. the output slew rate an d multiple drive strength controls are available in lvttl/lvcmos 3.3 v, lvcmos 2.5 v, lvcmos 2.5 v / 5.0 v input, lvcmos 1.8 v and lvcmos 1.5 v. all other i/o standards have a high output slew rate by default. for a3p030, refer to table 2-20 ; for other proasic3 devices, refer to table 2-21 for more information about the slew rate and drive strength specification. table 2-20 a3p030 i/o standards? out_drive settings i/o standards out_drive (ma) 248 lvttl/lvcmos33 ??? lvcmos25 ??? lvcmos25_50 ??? lvcmos18 ?? ? lvcmos15 ?? ? table 2-21 proasic3 device i/o standard s?slew and out_drive settings i/o standards out_drive (ma) 24681216 slew lvttl/lvcmos33 ?????? high low lvcmos25 ????? ? high low lvcmos25_50 ????? ? high low lvcmos18 ???? ? ? high low lvcmos15 ?? ? ? ? ? high low
proasic3 flash family fpgas 2-44 advanced v0.2 user i/o naming convention due to the comprehensive and flexible na ture of the proasic3 device user i/os, a naming scheme is used to show the details of the i/o ( figure 2-36 and figure 2-37 on page 2-45 ). the name identifies to whic h i/o bank it belongs, as well as the pairing and pin polar ity for differential i/os. i/o nomenclature = gmn/iouxwby gmn is only used for i/os that also have ccc access ? i.e., global pins. g=global m = global pin location associated with each ccc on the device: a (northwest corner), b (northeas t corner), c (east middle), d (southeast corner), e (southwest corner), and f (west middle). n = global input mux and pin number of the associated global location m, either a0, a1,a2, b0, b1, b2, c0, c1, or c2. figure 2-15 on page 2-16 shows the three input pins per each cl ock source mux at the ccc location m. u = i/o pair number in the bank, starting at 00 fr om the northwest i/o bank in a clockwise direction. x = p (positive) or n (negative) for di fferential pairs, or s (single-ended) for the i/o that suppo rt single-ended and voltage-referenced i/o standards only w = d (differential pair) or p (pair) or s (single-ended). d (differential pair) if both me mbers of the pair are bonded out to adjacent pins or are separated only by one gnd or nc pin; p (pair) if both members of the pair are bonded out but do not meet the adjacency requirement; or s (singl e-ended) if the i/o pair is not bonded out. for differential (d) pairs, adjacency for ball grid pa ckages means only vertical or horizontal. diagonal adjacency does not meet the requiremen ts for a true differential pair. b = bank y = bank number [0..3]. bank number starting at 0 fr om the northwest i/o bank in a clockwise direction. note: the a3p030 device does not support pll (v complf and v ccplf pins). figure 2-36 naming conventions of proasic3 devices with two i/o banks ccc "a" ccc "e" ccc/pll "f" ccc "b" ccc "d" ccc "c" a3p030 A3P060 a3p125 gnd v cc gnd v cci b1 v cc gnd v cci b0 bank 1 bank 1 bank 0 bank 0 bank 1 bank 0 v complf v ccplf gnd v cc v cci b1 gnd gnd v cc v cci b0 gnd vmv1 gndq gnd gnd v cci b1 v cci b2 v cc v cci b1 v cc gnd vmv2 gndq gnd tck tdi tms v jtag trst tdo v pump gnd gnd gndq vmv0 gnd vcc gnd v cci b0 v cci b0 vcc v cci b0 gnd vmv0 gndq
proasic3 flash family fpgas advanced v0.2 2-45 figure 2-37 naming conventions of proasic3 devices with four i/o banks a3p250 a3p400 a3p600 a3p1000 gnd vcc gnd v cci b3 bank 3 bank 3 bank 1 bank 1 bank 2 bank 0 v complf v ccplf gnd v cc v cci b3 gnd vmv3 gndq gnd gnd v cci b2 v cci b2 v cc v cci b2 v cc gnd vmv2 gndq gnd tck tdi tms v jtag trst tdo v pump gnd gnd v cc v cci b1 gnd v cc gnd v cci b1 gnd gndq vmv1 v cc v cci b0 gnd v cc v cci b0 gnd v cci b0 gnd vmv0 gndq ccc "a" ccc "e" ccc/pll "f" ccc "b" ccc "d" ccc "c"
proasic3 flash family fpgas 2-46 advanced v0.2 pin descriptions supply pins gnd ground ground supply volt age to the core, i/o outputs, and i/o logic. gndq ground (quiet) quiet ground supply voltage to input buffers of i/o banks. within the package, the gndq plane is decoupled from the simultaneous switching noise originated from the output buffer ground domain. this minimizes the noise transfer within the package, and improves input signal integr ity. gndq needs to always be connected on the board to gnd. v cc core supply voltage supply voltage to the fpga core, nominal 1.5 v. v cci bx i/o supply voltage supply voltage to the bank 's i/o output buffers and i/o logic. bx is the i/o bank number. there are eight i/o banks on proasic3 devices plus a dedicated v jtag bank. each bank can have a separate v cci connection. all i/os in a bank will run off the same v cci bx supply. v cci can be 1.5 v, 1.8 v, 2.5 v, or 3.3 v nominal voltage. unused i/o banks should have their corresponding v cci pins tied to gnd. vmvx i/o supply voltage (quiet) quiet supply voltage to th e input buffers of each i/o bank. x is the bank number. within the package, the vmv plane is decoupled from the simultaneous switching noise originated from the output buffer v cci domain. this minimizes the noise transfer within the package, and improves input signal integrity. each bank must have at least one vmv connection. all i/os in a bank run off the same vmvx supply. vmv is used to provide a quiet supply volt age to the input buffers of each i/o bank. vmvx can be 1.5 v, 1.8 v, 2.5 v, or 3.3 v nominal voltage. unused i/o banks should have their corresponding vmv pins tied to gnd. vmv and v cci should be at the same voltage within a given i/o bank. used vmv pins must be connected to the corresponding v cci pins of the same bank (i.e. vmv0 to v cci b0, vmv1 to v cci b1, etc.). v ccplf pll supply voltage 6 supply voltage to analog pll. if unused, v ccplf should be tied to gnd. v complf pll ground 6 ground to analog pll. unused v compl pins should be connected to gnd. v jtag jtag supply voltage proasic3 devices have a separate bank for the dedicated jtag pins. the jtag pins can be run at any voltage from 1.5 v to 3.3 v (nominal). is olating the jtag power supply in a separate i/o bank gives greater flexibility with supply selection and simplifies power supply and printed circuit board design. v pump programming supply voltage proasic3 devices support single-voltage isp programming of the configuration flash and from. for programming, v pump should be 3.3 v nominal. during normal device operation, v pump can be left floating or can be tied (pulled up) to any voltage between 0 v and 3.6 v. global pins gl globals gl i/os have access to certai n clock conditioning circuitry (and the pll) and/or have direct access to the global network (spines). additionally, the global i/os can be used as i/os, since they have identical capabilities. see more detailed descriptions of global i/o connectivity in the "clock conditioning circuits" section on page 2-13 . refer to the "user i/o naming convention" section on page 2-44 for a description of naming of global pins. jtag pins tck test clock test clock input for the jtag boundary-scan, isp, and ujtag usage. per the (jtag) ieee1532 specification, it is recommended that tck be tied to gnd or v jtag when not used. this prevents a pos sible totem-pole current on the input buffer stage. the tck pin does not have an internal weak pull-up resistor. tdi test data input serial input for jtag boundary-scan, isp, and ujtag usage. there is an internal weak pull-up resistor on the tdi pin. tdo test data output serial output for jtag boundary-scan, isp, and ujtag usage. the tdo pin does not have an internal weak pull- up resistor. 6. the a3p030 device does not support this feature.
proasic3 flash family fpgas advanced v0.2 2-47 tms test mode select the tms pin controls the use of the ieee1532 boundary scan pins (tck,tdi, tdo, trst). there is an internal weak pull-up resistor on the tms pin. trst boundary scan reset pin the trst pin functions as an active low input to asynchronously initialize (o r reset) the boundary scan circuitry. there is an internal weak pull-up resistor on the trst pin. in the operating mode, a 100 ? external pull- down resistor should be pl aced between trst and gnd to ensure that the chip does not switch into a different mode. special function pins nc no connect this pin is not connected to circuitry within the device. these pins can be driven to any voltage or can be left floating with no effect on the operation of the device. dc don't connect this pin should not be connected to any signals on the printed circuit board (pcb). these pins should be left un- connected. software tools overview of tools flow the proasic3 family of fpgas is fully supported by both actel libero ide and designer fpga development software. actel libero ide is an integrated design manager that seamlessly integrates design tools while guiding the user through the design flow, managing all design and log files, and passing necessary design data among tools. additionally, libero ide allows users to integrate both schematic and hdl synthesis into a single flow and verify the entire design in a single environment (see the libero ide flow diagram located on the actel website). libero ide includes synplify ? ae from synplicity ? , viewdraw ? ae from mentor graphics ? , model sim ? hdl simulator from mentor graphics, waveformer lite? ae from synapticad ? , palace? physical synthesis from magma design automation?, and designer software from actel. actel designer software is a place-and-route tool and provides a comprehensive suite of back-end support tools for fpga development. the designer software includes the following: timer ? a world-class integrated static timing analyzer and constrain ts editor that supports timing-driven place-and-route netlistviewer ? a design netlist schematic viewer chipplanner ? a graphical floorplanner viewer and editor smartpower ? tool which enables the designer to quickly estimate the power consumption of a design pineditor ? a graphical ap plication for editing pin assignments an d i/o attributes i/o attribute editor ? to ol which displays all assigned and unassigne d i/o macros and their attributes in a spreadsheet format with the designer software, a user can lock the design pins before layout while minimally impacting the results of place-and-route. additionally, actel back-annotation flow is compatible with all the major simulators. another tool included in the design er software is the actgen core generator, which easily creates popular and commonly used logic functions for implementation into your schematic or hdl design. actel designer software is compatible with the most popular fpga design entry and verification tools from eda vendors, such as ment or graphics, synplicity, synopsys, and cadence ? . the designer software is available for both the windows ? and unix operating systems. programming programming can be performed using various programming tools, such as silicon sc ulptor ii (bp micro systems) or flashpro3 (actel). the user can generate *.stp programming files from the designer software and can us e these files to program a device. proasic3 devices can be programmed in system. for more information on isp of proasic3 devices, refer to the in-system programming (isp) in proasic3/e using flashpro3 and programming a proasic3/e using a microprocessor application notes. security proasic3 devices have a built-in 128-bit aes decryption core (except the a3p030 device). the decryption core facilitates secure, in-sys tem programming of the fpga core array fabric and the from. the from and the fpga core fabric can be programmed independently from each other, allowing the from to be updated without the need for change to the fpga core fabric. the aes master key is stored in on-chip nonv olatile memory (flash). the aes master key can be preloaded into parts in a secure programming environment (such as the actel in-house programming center) and th en "blank" parts can be
proasic3 flash family fpgas 2-48 advanced v0.2 shipped to an untrusted programming or manufacturing center for final personalization with an aes encrypted bitstream. late stage product changes or personalization can be implemented easily and securely by simply sending a stapl file with aes encrypted data. secure remote field updates over public networks (such as the internet) are possible by sending and programming a stapl file with aes encrypted data. 128-bit aes decryption 7 the 128-bit aes standard (fips-192) block cipher is the nist (national institute of standards and technology) replacement for the des (data encryption standard fips46-2). aes has been desi gned to protect sensitive government information well into the 21st century. it will replace the aging des, which nist adopted in 1977 as a federal information pr ocessing standard used by federal agencies to protec t sensitive, unclassified information. the 128-bit aes standard has 3.4x10 38 possible 128-bit key variants, and it has been estimated that it would take 1,000 tr illion years to crack 128-bit aes cipher text using exhaustive techniques. keys are stored (securely) in proasic3 devices in nonvolatile flash memory. all programming files sent to the device can be authenticated by the part prior to programming to ensure that bad programming data is not loaded into the part that may possibly damage it. all programming verification is performed on-chip, ensuring that the contents of proasic3 devices remain secure. aes decryption can also be used on the 1,024-bit from to allow for secure remote updates of the from contents. this allows for easy, secure support for subscription model products. see the application note, proasic3/e security , for more details. isp proasic3 devices support ieee1532 isp via jtag and require a single v pump voltage of 3.3 v during programming. in addition, programming via a microcontroller (mcu) in a target system can be achieved. see the application note in-system programming (isp) in proasic3/e using flashpro3 for more details. jtag 1532 programming proasic3 devices support the jtag-based ieee1532 standard for isp. as part of this support, when a proasic3 device is in an unprogrammed state, all user i/o pins are disabled. this is achieved by keeping the global io_en signal deactivated, which also has the effect of disabling the input buffers. consequent ly, the sample instruction will have no effect while the proasic3 device is in this unprogrammed state. this is different behavior from that observed in the proasic plus device family. this lack of effect is necessitated by the fact that sample is defined in the ieee1532 specif ication as a noninvasive instruction. if the input buffers were to be enabled by sample temporarily turning on the i/os, then it would not truly be a noninvasive instruction, hence the lack of effect when the proasic3 device is in this unprogrammed state. refer to the standard or the in- system programming (isp) in proasic3/e using flashpro3 application note for more details. boundary scan proasic3 devices are comp atible with ieee standard 1149.1, which defines a hardware architecture and the set of mechanisms for boundary-scan testing. the basic proasic3 boundary-scan logic circuit is composed of the tap (test access port) controller, test data registers, and instruction register ( figure 2-38 on page 2-49 ). this circuit supports all mand atory ieee 1149.1 instructions (extest, sample/preload, and bypass) and the optional idcode instruction ( table 2-22 on page 2-49 ). each test section is accessed through the tap, which has five associated pins: tck (t est clock input), tdi, and tdo (test data input and output), tms (test mode selector), and trst (test reset input). tms, tdi, and trst are equipped with pull-up resistors to ensure proper operation when no input data is supplied to them. these pins are dedicated for boundar y-scan test usage. actel recommends that a nominal 20 k ? pull-up resistor be added to tdo and tck pins. the tap controller is a 4-bit state machine (16 states) th at operates as shown in figure 2-38 on page 2-49 . the 1s and 0s represent the values that must be present at tms at a rising edge of tck for the given state tran sition to occur. ir and dr indicate that the instruction register or the data register is operating in that state. proasic3 devices have to be programmed at least once for complete boundary-scan functionality to be available. if boundary-scan func tionality is required prior to partial programming, refer to online technical support on the actel website and s earch for proasic3 bsdl. the tap controller receives two control inputs (tms and tck) and generates control and clock signals for the rest of the test logic architec ture. on power-up, the tap controller enters the test-log ic-reset state. to guarantee a reset of the controller from any of the possible states, tms must remain high for fi ve tck cycles. the trst pin 7. the a3p030 device does not support aes decryption.
proasic3 flash family fpgas advanced v0.2 2-49 may also be used to asyn chronously place the tap controller in the test-logic-reset state. proasic3 devices support three types of test data registers: bypass, device identification, and boundary scan. the bypass register is selected when no other register needs to be accessed in a device. this speeds up test data transfer to other devices in a test data path. the 32-bit device identification register is a shift register with four fields (lowest significant byte (lsb), id number, part number, and version). the boundary-scan register observes and contro ls the state of each i/o pin. each i/o cell has three boundary-scan register cells, each with a serial-in, serial-out, parallel-in, and parallel-out pin. the serial pins are used to serially connect all the boundary-scan register cells in a device into a boundary- scan register chain, which st arts at the tdi pin and ends at the tdo pin. the parallel ports are connected to the internal core logic i/o tile and the input, output, and control ports of an i/o buffer to capture and load data into the register to control or observe the logic state of each i/o. figure 2-38 boundary-scan chain in proasic3 device logic tdi tck tms trst tdo i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o bypass register instruction register tap controller test data registers table 2-22 boundary-scan opcodes hex opcode extest 00 highz 07 usercode 0e sample/preload 01 idcode 0f clamp 05 bypass ff

proasic3 flash family fpgas advanced v0.2 3-1 dc and switching characteristics general specifications dc and switching characteristics for ?f speed grade targets based only on simulation. the characteristics provided for ?f speed grade are subject to change after establishing fpga specifications. some restrictions might be added and will be reflected in futu re revisions of this documen t. the ?f speed grade is only supported in commerci al temperature range. operating conditions stresses beyond those listed in the table 3-1 may cause permanent damage to the device. exposure to absolute maximum rated cond itions for extended periods may affect device reliability. devices should not be operated outside the recommended operating ranges specified in table 3-2 on page 3-2 . table 3-1 absolute maximum ratings symbol parameter limits units v cc dc core supply voltage ?0.3 to 1.65 v v jtag jtag dc voltage ?0.3 to 3.75 v v pump programming voltage ?0.3 to 3.75 v v ccpll analog power supply (pll) ?0.3 to 1.65 v v cci dc i/o output buffer supply voltage ?0.3 to 3.75 v vmv dc i/o input buffer supply voltage ?0.3 to 3.75 v vi i/o input voltage ?0.3 v to 3.6 v (when i/o hot insertion mode is enabled) ?0.3 v to (v cci + 1 v) or 3.6 v, whichever voltage is lower (when i/o hot-insertion mode is disabled) v notes: 1. device performance is not guaranteed if storage temperature exceeds 110c. 2. the device should be operated within the limits specified by the datasheet. during transitions, the input signal may undersho ot or overshoot according to the limits shown in table 3-3 on page 3-2 .
proasic3 flash family fpgas 3-2 advanced v0.2 table 3-2 recommended operating conditions symbol parameter comme rcial industrial units t a ambient temperature 0 to +70 -40 to +85 c v cc 1.5 v dc core supply voltage 1.425 to 1.575 1.425 to 1.575 v v jtag jtag dc voltage 1.4 to 3.6 1.4 to 3.6 v v pump programming voltage programming mode 3.0 to 3.6 3.0 to 3.6 v operation 3 0 to 3.6 0 to 3.6 v v ccpll analog power supply (pll) 1.4 to 1.6 1.4 to 1.6 v v cci and vmv 1.5 v dc supply voltage 1.425 to 1.575 1.425 to 1.575 v 1.8 v dc supply voltage 1.7 to 1.9 1.7 to 1.9 v 2.5 v dc supply voltage 2.3 to 2.7 2.3 to 2.7 v 3.3 v dc supply voltage 3.0 to 3.6 3.0 to 3.6 v lvds differential i/o 2.375 to 2.625 2.375 to 2.625 v lvpecl differential i/o 3.0 to 3.6 3.0 to 3.6 v notes: 1. the ranges given here are for power supplie s only. the recommended input voltage ranges specific to each i/ o standard are giv en in table 3-13 on page 3-14 . vmv and v cci should be at the same voltage within a given i/o bank. 2. all parameters representing voltages are measured with respect to gnd un less otherwise specified. 3. v pump can be left floating during operation (not programming mode). table 3-3 overshoot and undershoot limits (as measured on quiet i/os) 1 v cci and vmv average v cci -gnd overshoot or undershoot duration as percentage of clock cycle 2 maximum overshoot/ undershoot 2 2.7 v or less 10% 1.4 v 5% 1.49 v 3 v 10% 1.1 v 5% 1.19 v 3.3 v 10% 0.79 v 5% 0.88 v 3.6 v 10% 0.45 v 5% 0.54 v notes: 1. based on reliability requirements at 85c. 2. the duration is allowed at one cycle out of six clock cycles (estimated sso density over cycles). if the overshoot/undershoot occurs at one out of two cycles, then the maximum overs hoot/undershoot has to be reduced by 0.15 v. table 3-4 flash programming, storag e, and operating limits product grade programming cycles program retention storage temperature maximum operating junction temperature t j (c) min. max. commercial 500 20 years 0 110 110 industrial 500 20 years ?40 110 110 note: this is a stress rating only. functional operation at any other condition other than thos e indicated is not implied.
proasic3 flash family fpgas advanced v0.2 3-3 i/o power-up and supply voltage thresholds for power-on reset (commercial and industrial) sophisticated power-up management circuitry is designed into every proasi c3 device. these circuits ensure easy transition from the powered-off state to the powered-up state of the device. the many different supplies can power-up in any sequence with minimized current spikes or su rges. in addition, the i/o will be in a known state through the power-up sequence. the basic principle is shown in figure 3-1 . there are five regions to consider during power-up. proasic3 i/os are activated only if all of the following three conditions are met: 1. v cc and v cci are above the minimum specified trip points ( figure 3-1 ) 2. v cci > v cc ? 0.75 v (typ) 3. chip is in the operating mode v cci trip point: ramping up: 0.6 v < trip_point_up <1.2 v ramping down: 0.5 v < trip_point_down < 1.1 v v cc trip point: ramping up: 0.6 v < trip_point_up <1.1 v ramping down: 0.5 v < trip_point_down < 1 v v cc and v cci ramp-up trip poin ts are about 100 mv higher than ramp-down trip points. this specifically built-in hysteresis prevents undesirable power-up oscillations and current su rges. note the following: during programming, i/os become tristated and weakly pulled up to v cci . jtag supply, pll power supplies, and charge pump v pump supply have no influence on i/o behavior. internal power-up activation sequence 1. core 2. input buffers 3. output buffers: after 200 ns delay from input buffer activation. figure 3-1 i/o state as a function of v cci and v cc voltage levels region 1: i/o buffers are off region 2: i/o buffers are on. i/os are functional (except differential inputs) but slower because v cci /v cc are below specification. for the same reason, input buffers do not meet v ih /v il levels, and output buffers do not meet v oh /v ol levels. min v cci datasheet specification voltage at a selected i/o standard; i.e., 1.425 v or 1.7 v or 2.3 v or 3.0 v v cc v cc = 1.425 v region 1: i/o buffers are off activation trip point: v a = 0.85 v 0.25 v deactivation trip point: v d = 0.75 v 0.25 v activation trip point: v a = 0.9 v 0.3 v deactivation trip point: v d = 0.8 v 0.3 v v cc = 1.575 v region 5: i/o buffers are on and power supplies are within specification. i/os meet the entire datasheet and timer specifications for speed, v ih /v il , v oh /v ol , etc. region 4: i/o buffers are on. i/os are functional (except differential but slower because v cci is below specifcation. for the same reason, input buffers do not meet v ih /v il levels, and output buffers do not meet v oh /v ol levels. region 4: i/o buffers are on. i/os are functional (except differential inputs) where vt can be from 0.58 v to 0.9 v (typically 0.75 v) v =v + vt cc cci v cci region 3: i/o buffers are on. i/os are functional; i/o dc specifications are met, but i/os are slower because the v cc is below specification
proasic3 flash family fpgas 3-4 advanced v0.2 thermal characteristics introduction the temperature variable in the actel designer software refers to the junction te mperature, not the ambient temperature. this is an im portant distinction because dynamic and static power consumption cause the chip junction to be higher than the ambient temperature. eq 3-1 can be used to calculate junction temperature. t j = junction temperature = ? t + t a eq 3-1 where t a = ambient temperature ? t = temperature gradient between junction (silicon) and ambient ? t = ja * p ja = junction-to-ambient of the package. ja numbers are located in table 3-5 . p = power dissipation package thermal ch aracteristics the device junction-to-case thermal resistivity is jc and the junction-to-ambient air thermal resistivity is ja . the thermal characteristics for ja are shown for two air flow rates. the absolute maximum junction temperature is 110c. eq 3-2 shows a sample calcul ation of the absolute maximum power dissipation allowed for a 484-pin fbga package at commercial temperature and still air. eq 3-2 temperature and voltage derating factors table 3-5 package thermal resistivities package type pin count jc ja units still air 200 ft./min. 500 ft./min. quad flat no lead (qfn) 132 13.2 28.9 24.6 23.1 c/w very thin quad flat pack (vqfp) 100 10.0 35.3 29.4 27.1 c/w thin quad flat pack (tqfp) 144 11.0 33.5 28.0 25.7 c/w plastic quad flat package (pqfp) 208 8.0 26.1 22.5 20.8 c/w plastic quad flat package (pqfp) with embedded heat spreader 208 3.8 16.2 13.3 11.9 c/w fine pitch ball grid array (fbga) 144 3.8 26.9 22.9 21.5 c/w 256 3.8 26.6 22.8 21.5 c/w 484 3.2 20.5 17.0 15.9 c/w table 3-6 temperature and voltage derati ng factors for timing delays (normalized to t j = 70c, v cc = 1.425 v) array voltage v cc (v) junction temperature (c) ?40c 0c 25c 70c 85c 110c 1.425 0.88 0.93 0. 95 1.00 1.02 1.05 1.500 0.83 0.87 0. 89 0.94 0.96 0.98 1.575 0.79 0.84 0. 86 0.91 0.92 0.94 maximum power allowed max. junction temp. ( c) max. ambient temp. ( c) ? ja ( c/w) ------------------------------------------------------------------------------------------------------------------------------- -------- 150 c70 c ? 20.5 c/w ------------------------------------ 3.90 w = = =
proasic3 flash family fpgas advanced v0.2 3-5 calculating power dissipation quiescent supply current power per i/o pin table 3-7 quiescent supply current characteristics a3p030 A3P060 a3p125 a3p250 a3p400 a3p600 a3p1000 static i dd 1 10 ma 10 ma 10 ma 20 ma 20 ma 30 ma 70 ma notes: 1. i dd includes v cc , v pump , v cci , and vmv currents in industrial temperature ra nges (junction temperature from ?40c to 85c). values do not include i/o static contribution, which is shown in table 3-8 and table 3-9 . 2. ?f speed grade devices may experience higher standby i dd of up to five times the standard i dd and higher i/o leakage. table 3-8 summary of i/o input buffer power (per pin) ? default i/o software settings vmv (v) static power p dc2 (mw) 1 dynamic power p ac9 (w/mhz) 2 single-ended 3.3 v lvttl / 3.3 v lvcmos 3.3 ? 16.69 2.5 v lvcmos 2.5 ? 5.12 1.8 v lvcmos 1.8 ? 2.13 1.5 v lvcmos (jesd8-11) 1.5 ? 1.45 3.3 v pci 3.3 ? 18.11 3.3 v pci-x 3.3 ? 18.11 differential lvds 2.5 2.26 1.20 lvpecl 3.3 5.72 1.87 notes: 1. p dc2 is the static power (where applicable) measured on vmv. 2. p ac9 is the total dynamic power measured on v cc and vmv. table 3-9 summary of i/o output buffer power (per pin) ? default i/o software settings 1 c load (pf) v cci (v) static power p dc3 (mw) 2 dynamic power p ac10 (w/mhz) 3 single-ended 3.3 v lvttl / 3.3 v lvcmos 35 3.3 ? 468.67 2.5 v lvcmos 35 2.5 ? 267.48 1.8 v lvcmos 35 1.8 ? 138.32 1.5 v lvcmos (jesd8-11) 35 1.5 ? 96.13 3.3 v pci 10 3.3 ? 201.02 3.3 v pci-x 10 3.3 ? 201.02 differential lvds ? 2.5 7.74 88.92 lvpecl ? 3.3 19.54 166.52 notes: 1. dynamic power consumption is given for standard load and software default drive strength and output slew. 2. p dc3 is the static power (where applicable) measured on v cci . 3. p ac10 is the total dynamic power measured on v cc and v cci .
proasic3 flash family fpgas 3-6 advanced v0.2 power consumption of vari ous internal resources table 3-10 different componen ts contributing to dy namic power consumption in proasic3 devices parameter definition device specific dynamic power ( w/mhz) a3p250 p ac1 clock contribution of a global rib 100 p ac2 clock contribution of a global spine 10 p ac3 clock contribution of a versatile row 1.00 p ac4 clock contribution of a versatile used as a sequential module 0.00 p ac5 first contribution of a versatile used as a sequential module 0.07 p ac6 second contribution of a versatile used as a sequential module 0.29 p ac7 contribution of a versatile used as a combinatorial module 0.29 p ac8 average contribution of a routing net 0.70 p ac9 contribution of an i/o inpu t pin (standard dependent) see table 3-7 on page 3-5 . p ac10 contribution of an i/o outpu t pin. (standard dependent) see table 3-8 on page 3-5 p ac11 average contribution of a ram block during a read operation 25.00 p ac12 average contribution of a ram block during a write operation 30.00 p ac13 first contribution of a pll 4.00 p ac14 second contribution of a pll 2.00 note: *for a different output load, dr ive strength, or slew rate, ac tel recommends using the actel power spreadsheet calculator or smartpower tool in libero ide software.
proasic3 flash family fpgas advanced v0.2 3-7 power calculation methodology the section below describes a simplified method to estimate power consumption of an application. for more accurate and detailed power estimations, use the smartpower tool in actel libero ide software. the power calculation methodology described below uses the following variables: the number of plls as well as the number and the frequency of each output clock generated the number of combinatorial and se quential cells used in the design the internal clock frequencies the number and the standard of i/o pins used in the design the number of ram blocks used in the design toggle rates of i/o pins as well as versatiles?guidelines are provided in table 3-11 on page 3-9 enable rates of output buffers?guidelines are provided for typical applications in table 3-12 on page 3-9 read rate and write rate to the memory?guidelin es are provided for typical applications in table 3-12 on page 3-9 . the calculation should be repeated for each clock domain defined in the design. methodology total power consumption?p total p total = p stat + p dyn p stat is the total static power consumption. p dyn is the total dynamic power consumption. total static power consumption?p stat p stat = p dc1 + n inputs * p dc2 + n outputs * p dc3 n inputs is the number of i/o input buffers used in the design. n outputs is the number of i/o output buffers used in the design. total dynamic power consumption?p dyn p dyn = p clock + p s-cell + p c-cell + p net + p inputs + p outputs + p memory + p pll global clock contribution?p clock p clock = (p ac1 + n spine *p ac2 + n row *p ac3 ) * f clk n spine is the number of global spines used in the user design?guideline are provided in table 3-11 on page 3-9 . n row is the number of versatile rows used in the desi gn?guidelines are provided in table 3-11 on page 3-9 . f clk is the global clock signal frequency. if the number of spines an d rows is not known, use the simplified formula below: p clock = (p ac1 + n s-cell *p ac4 ) * f clk n s-cell is the number of versatiles used as sequential modules in the design. f clk is the global clock signal frequency. sequential cells contribution?p s-cell p s-cell = n s-cell * (p ac5 + 1 * p ac6 ) * f clk n s-cell is the number of versatiles used as sequential modules in the design . when a multi-tile sequential cell is used, it should be accounted for as 1. 1 is the toggle rate of versatile outputs?guidelines are provided in table 3-11 on page 3-9 . f clk is the global clock signal frequency.
proasic3 flash family fpgas 3-8 advanced v0.2 combinational cells contribution?p c-cell p c-cell = n c-cell * 1 * p ac7 *f clk n c-cell is the number of versatiles used as combinatorial modu les in the design. 1 is the toggle rate of versatile outputs?guidelines are provided in table 3-11 on page 3-9 . f clk is the global clock signal frequency. routing net contribution?p net p net = (n s-cell + n c-cell ) * 1 * p ac8 * f clk n s-cell is the number versatiles used as sequential modules in the design. n c-cell is the number of versatiles used as combinatorial modu les in the design. 1 is the toggle rate of versatile outputs?guidelines are provided in table 3-11 on page 3-9 . f clk is the global clock signal frequency. i/o input buffer contribution?p inputs p inputs = n inputs * 2 * p ac9 * f clk n inputs is the number of i/o input buffers used in the design. 2 is the i/o buffer toggle rate ?guidelines are provided in table 3-11 on page 3-9 . f clk is the global clock signal frequency. i/o output buffer contribution?p outputs p outputs = n outputs * 2 * 1 * p ac10 * f clk n outputs is the number of i/o output buffers used in the design. 2 is the i/o buffer toggle rate ?guidelines are provided in table 3-11 on page 3-9 . 1 is the i/o buffer enable rate ?guidelines are provided in table 3-12 on page 3-9 . f clk is the global clock signal frequency. ram contribution?p memory p memory = p ac11 * n blocks * f read-clock * 2 + p ac12 * n block * f write-clock * 3 n blocks is the number ram blocks used in the design. f read-clock is the memory read clock frequency. 2 is the ram enable rate for read operations. f write-clock is the memory write clock frequency. 3 the ram enable rate for write oper ations?guidelines are provided in table 3-12 on page 3-9 . pll/ccc contribution?p pll p pll = p ac13 * f clkin + p ac14 *f clkout f clkin is the input clock frequency. f clkout is the output clock frequency. 1 1. the pll dynamic contribution depends on the input clock freq uency, the number of output clock signals generated by the pll, and the frequency of each output cloc k. if a pll is used to generate more than one output clock, include each output clock in the formula by adding its corresponding contribution (p ac14 *f clkout product) to the total pll contribution.
proasic3 flash family fpgas advanced v0.2 3-9 guidelines toggle rate definition a toggle rate defines the frequency of a net or logic element relative to a clock. it is a percentage. if the toggle rate of a net is 100%, this means that this net switches at half the cloc k frequency. below are some examples: the average toggle rate of a shift-register is 100% because all flip-flop outputs toggle at half of the clock frequency. the average toggle rate of an 8-bit counter is 25%: ? bit 0 (lsb) = 100% ? bit 1 = 50% ? bit 2 = 25% ?? ? bit 7 (msb) = 0.78125% ? the average toggle rate is = (100% + 50% + 25% + 12.5% +...0.78125%) / 8. enable rate definition output enable rate is the average percentage of time during which tristate outputs are enabled. when nontristate output buffers are used, the enable rate should be 100%. table 3-11 toggle rate guidelines reco mmended for power calculation component definition guideline 1 toggle rate of versatile outputs 10% 2 i/o buffer toggle rate 10% table 3-12 enable rate guidelines recommended for power calculation component definition guideline 1 i/o output buffer enable rate 100% 2 ram enable rate for read operations 12.5% 3 ram enable rate for write operations 12.5%
proasic3 flash family fpgas 3-10 advanced v0.2 user i/o characteristics timing model figure 3-2 timing model operating conditions: ?2 speed, commercial temperature range (t j = 70c), worst case v cc =1.425 v dq y y dq dq dq y combinational cell combinational cell combinational cell i/o module (registered) i/o module (non-registered) buffer register cell register cell i/o module (registered) i/o module (non-registered) lvpecl lvpecl lvds lvttl 3.3 v output drive strength = 12 m a high slew rate y combinational cell y combinational cell y combinational cell buffer i/o module (non-registered) lvttl output drive strength = 8 ma high slew rate i/o module (non-registered) lvcmos 1.5v output drive strength = 4 ma high slew rate lvttl output drive strength = 12 ma high slew rate i/o module (non-registered) input lvttl clock t pd = 0.54 ns t pd =0.47 ns t pd = 0.85 ns t py = 1.05 ns t py = 0.76 ns t py = 1.20 ns t dp = 2.64 ns t iclkq = 0.63 ns t isud = 0.43 ns t clkq = 0.53 ns t sud = 0.40 ns t clkq = 0.53 ns t sud = 0.40 ns t dp = 1.34 ns input lvttl clock input lvttl clock t pd = 0.49 ns t pd = 0.46 ns t pd = 0.46 ns t py = 0.76 ns t py = 0.76 ns t dp = 3.66 ns t dp = 3.97 ns t dp = 2.64 ns t oclkq = 0.63 ns t osud = 0.43 ns
proasic3 flash family fpgas advanced v0.2 3-11 figure 3-3 input buffer timing mode l and delays (example) t py = max(t py (r), t py (f)) t pys = max(t pys (r), t pys (f)) t din = max(t din (r), t din (f)) t py (r) pad y v trip gnd t py (f) v trip 50% 50% v ih v cc v il t pys (r) t pys (f) t dout (r) din gnd t dout (f) 50% 50% v cc pad y t py t pys d clk q i/o interface din t din to array
proasic3 flash family fpgas 3-12 advanced v0.2 figure 3-4 output buffer model and delays (example) (f)) t dp (r) pad v ol t dp (f) v trip v trip v oh v cc d 50% 50% v cc 0 v dout 50% 50% 0 v t dout (r) t dout (f) from array pad t dp t dp = max(t dp (r), t dp (f)) std load d clk q i/o interface dout d t dout t dout = max(t dout (r), t dout
proasic3 flash family fpgas advanced v0.2 3-13 figure 3-5 tristate output buffer timing model and delays (example) d clk q d clk q 10% v cci cci t zl v trip 50% t hz 90% v cci t zh v trip 50% 50% t lz 50% eout pad d e 50% t eout (r) 50% t eout (f) pad dout eout t zl ,t zh ,t hz ,t lz , t , t zls zhs d i/o interface e t eout = max(t eout (r), t eout (f)) t eout t zls v trip 50% t zhs v trip 50% eout pad d e 50% 50% t eout (r) t eout (f) 50% v cc vcc vcc v v v vcc v oh v ol v ol cc cc
proasic3 flash family fpgas 3-14 advanced v0.2 overview of i/o performance summary of i/o dc input and output levels ? de fault i/o software settings summary of i/o ti ming characteristics ? default i/o software settings table 3-13 summary of maximum and mini mum dc input and ou tput levels applicable to commercial and industrial conditions i/o standard drive strength slew rate v il v ih v ol v oh i ol i oh min, v max, v min, v max, v max, v min, v ma ma 3.3 v lvttl / 3.3 v lvcmos 12 ma high ?0.3 0.8 2 3.6 0.4 2.4 12 12 2.5 v lvcmos 12 ma high ?0.3 0.7 1.7 3.6 0.7 1.7 12 12 1.8 v lvcmos 8 ma high ?0.3 0.35 * v cci 0.65 * v cci 3.6 0.45 v cci ? 0.45 8 8 1.5 v lvcmos 4 ma high ?0.3 0.30 * v cci 0.7 * v cci 3.6 0.25 * v cci 0.75 * v cci 44 3.3 v pci per pci specifications 3.3 v pci-x per pci-x specifications note: currents are measured at 85c junction temperature. table 3-14 summary of maximum and minimum dc input levels applicable to comme rcial and industrial conditions dc i/o standards commercial 1 industrial 2 i il i ih i il i ih a a a a 3.3 v lvttl /3.3v lvcmos 10 10 15 15 2.5 v lvcmos 10 10 15 15 1.8 v lvcmos 10 10 15 15 1.5 v lvcmos 10 10 15 15 3.3 v pci 10101515 3.3 v pci-x 10101515 notes: 1. commercial range (0c < t j < 70c) 2. industrial range (?40c < t j < 85c) table 3-15 summary of ac measuring points standard measuring trip point (v trip ) 3.3 v lvttl / 3.3 v lvcmos 1.4 v 2.5 v lvcmos 1.2 v 1.8 v lvcmos 0.90 v 1.5 v lvcmos 0.75 v 3.3 v pci 0.285 * v cci (rr) 0.615 * v cci (ff) 3.3 v pci-x 0.285 * v cci (rr) 0.615 * v cci (ff)
proasic3 flash family fpgas advanced v0.2 3-15 table 3-16 i/o ac parameter definitions parameter parameter definition t dp data to pad delay through the output buffer t py pad to data delay through the input buffer t dout data to output buffer de lay through the i/o interface t eout enable to output buffer tristate control delay through the i/o interface t din input buffer to data delay through the i/o interface t hz enable to pad delay through the output buffer?high to z t zh enable to pad delay through the output buffer?z to high t lz enable to pad delay through the output buffer?low to z t zl enable to pad delay through the output buffer?z to low t zhs enable to pad delay through the output buffer with delayed enable?z to high t zls enable to pad delay through the output buffer with delayed enable?z to low table 3-17 summary of i/o timing characte ristics?software default settings commercial-case conditions: t j = 70c, worst case v cc = 1.425 v, worst case v cci = 3.0 v i/o standard drive strength (ma) slew rate capacitive load (pf) external resistor t dout t dp t din t py teout t zl tzh t lz t hz t zls t zhs units 3.3 v lvttl / 3.3 v lvcmos 12 ma high 35 pf - 0.45 2.64 0.03 0.7 60.322.692.112.402.674.363.78 ns 2.5 v lvcmos 12 ma high 35pf - 0.452.660.030.980.322.712.562.472.574.384.23 ns 1.8 v lvcmos 8 ma high 35pf - 0.453.320.030.910.323.123.322.632.524.794.99 ns 1.5 v lvcmos 4 ma high 35pf - 0.453.970.031.070.323.623.972.792.545.295.64 ns 3.3 v pci per pci spec high 10pf 25 2 0.45 2.00 0.03 0.65 0.32 2.04 1.46 2.40 2.67 2.04 1.46 ns 3.3 v pci-x per pci-x spec high 10pf 25 2 0.45 2.00 0.03 0.65 0.32 2.04 1.46 2.40 2.67 2.04 1.46 ns lvds 24 ma high - - 0.45 1.36 0.03 1.20 - - - - - - - ns lvpecl 24 ma high - - 0.45 1.34 0.03 1.05 - - - - - - - ns notes: 1. for specific junction temperature and voltage-supply levels, refer to table 3-6 on page 3-4 for derating values. 2. resistance is used to measure i/o propagation delays as defined in pci specifications. see figure 3-10 on page 3-26 for connectivity. this resistor is not required during normal operation.
proasic3 flash family fpgas 3-16 advanced v0.2 detailed i/o dc characteristics table 3-18 input capacitance symbol definition conditions min. max. units c in input capacitance v in = 0, f = 1.0 mhz 8 pf c inclk input capacitance on the clock pin v in = 0, f = 1.0 mhz 8 pf table 3-19 i/o output buffer maximum resistances 1 standard drive strength r pull-down r pull-up ( ? ) 2 ( ? ) 3 3.3 v lvttl / 3.3 v lvcmos 4 ma 100 300 8 ma 50 150 12 ma 25 75 16 ma 25 75 2.5 v lvcmos 4 ma 100 200 8 ma 50 100 12 ma 25 50 1.8 v lvcmos 2 ma 200 225 4 ma 100 112 8 ma 50 56 1.5 v lvcmos 2 ma 200 224 4 ma 100 112 3.3 v pci/pci-x per pci/ pci-x specification 25 75 notes: 1. these maximum values are provided for informational reasons only. minimum output buffer resistance values depend on v cci , drive strength selection, temperature, and process. for board design considerations and detailed output buffer resistances, use the corresponding ibis models located on the actel website at http://www.actel.com/te chdocs/models/ibis.html . 2. r (pull-down-max) = (v olspec ) / i olspec 3. r (pull-up-max) = (v ccimax ? v ohspec ) / i ohspec table 3-20 i/o weak pull-up/pull-down resistances minimum and maximum we ak pull-up/pull-down resistance values v cci r (weak pull-up) 1 ( ? ) r (weak pull-down) 2 ( ? ) min. max. min. max. 3.3 v 10 k 45 k 10 k 45 k 2.5 v 11 k 55 k 12 k 74 k 1.8 v 18 k 70 k 17 k 110 k 1.5 v 19 k 90 k 19 k 140 k notes: 1. r (weak pull-up-max) = (v olspec ) / i (weak pull-up-min) 2. r (weak pull-up-max) = (v ccimax ? v ohspec ) / i (weak pull-up-min)
proasic3 flash family fpgas advanced v0.2 3-17 the length of time an i/o can withstand i osh /i osl events depends on the junction temperature. the reliability data below is based on a 3.3 v, 12 ma i/o setting, whic h is the worst case for this type of analysis. for example, at 110c, the short current condition would have to be sustained for more than three months to cause a reliability concern. the i/o design does not contain any short circuit protecti on, but such protec tion would only be needed in extremely prol onged stress conditions. table 3-21 i/o short currents i osh /i osl drive strength i osh (ma)* i osl (ma)* 3.3 v lvttl / 3.3 v lvcmos 4 ma 25 27 8 ma 51 54 12 ma 103 109 16 ma 103 109 2.5 v lvcmos 4 ma 16 18 8 ma 32 37 12 ma 65 74 1.8 v lvcmos 2 ma 9 11 4 ma 17 22 8 ma 35 44 1.5 v lcmos 2 ma 13 16 4 ma 25 33 note: *t j = 100c table 3-22 short current event du ration before failure temperature time before failure ?40c > 20 years 0c > 20 years 25c > 20 years 70c 5 years 85c 2 years 100c 6 months 110c 3 months table 3-23 i/o input rise time, fall time , and related i/o reliability input buffer input rise/fall time (min.) input rise/fall time (max.) reliability lvttl/lvcmos no requirement 10 ns (or more *) 20 years (110c) lvds/lvpecl no requirement 10 ns (or more *) 10 years (100c) note: *this limitation is related only to the noise induced into input buffer trace. if the noise is low, then the rise time and fall time of input buffers can be increased be yond the maximum value. the longer the rise/fall times, the more susceptible the input signal is to the board noise. actel recommends signal integrity evaluation/characterization of the system to ensure that there is no excessi ve noise coupling into input signals.
proasic3 flash family fpgas 3-18 advanced v0.2 single ended i/o characteristics 3.3 v lvttl / 3.3 v lvcmos low-voltage transistor-transistor logic (l vttl) is a general purpose standard (eia /jesd) for 3.3 v ap plications. it uses an lvttl input buffer and push-pull output buffer. table 3-24 minimum and maximum dc input and output levels 3.3 v lvttl/ 3.3 v lvcmos v il v ih v ol v oh i ol i oh i osl i osh i il i ih drive strength min, v max, v min, v max, v max, v min,v ma ma max, ma 1 max, ma 1 a 2 a 2 4 ma ?0.3 0.8 2 3.6 0.4 2.4 4 4 27 25 10 10 8 ma ?0.3 0.8 2 3.6 0.4 2.4 8 8 54 51 10 10 12 ma ?0.3 0.8 2 3.6 0.4 2.4 12 12 109 103 10 10 16 ma ?0.3 0.8 2 3.6 0.4 2.4 16 16 109 103 10 10 notes: 1. currents are measured at high temperature (100c junction temperature) and maximum voltage. 2. currents are measured at 85c junction temperature. 3. software default selection highlighted in gray. figure 3-6 ac loading table 3-25 ac waveforms, measuring poin ts and capacitive loads input low (v) input high (v) measuring point* (v) c load (pf) 03.31.435 note: *measuring point = v trip. see table 3-15 on page 3-14 for a complete table of trip points. test point test point enable path data path r to v for t /t /t cci lz zl zls 35 pf for t /t /t /t zh zhs zls zl 5 pf for t /t hz lz r to gnd for t /t /t hz zh zhs 35 pf r = 1 k
proasic3 flash family fpgas advanced v0.2 3-19 timing characteristics table 3-26 3.3 v lvttl / 3.3 v lvcmos low slew commercial-case conditions: t j = 70c, worst case v cc = 1.425 v, worst case v cci = 3.0 v drive strength (ma) speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 4 ma ?f 0.72 12.32 0.05 1.22 0.51 12.55 10.69 3.18 2.95 15.23 13.37 ns std. 0.60 10.26 0.04 1.02 0.43 10. 45 8.90 2.64 2.46 12.68 11.13 ns ?1 0.51 8.72 0.04 0.86 0.36 8. 88 7.57 2.25 2.09 10.79 9.47 ns ?2 0.45 7.66 0.03 0.76 0.32 7. 80 6.64 1.98 1.83 9.47 8.31 ns 8 ma ?f 0.72 8.74 0.05 1.22 0.51 8. 90 7.55 3.58 3.65 11.59 10.23 ns std. 0.60 7.27 0.04 1.02 0.43 7. 41 6.28 2.98 3.04 9.64 8.52 ns ?1 0.51 6.19 0.04 0.86 0.36 6. 30 5.34 2.54 2.59 8.20 7.25 ns ?2 0.45 5.43 0.03 0.76 0.32 5. 53 4.69 2.23 2.27 7.20 6.36 ns 12 ma ?f 0.72 6.70 0.05 1.22 0.51 6.83 5.85 3.85 4.10 9.51 8.54 ns std. 0.60 5.58 0.04 1.02 0.43 5. 68 4.87 3.21 3.42 7.92 7.11 ns ?1 0.51 4.75 0.04 0.86 0.36 4. 83 4.14 2.73 2.90 6.74 6.04 ns ?2 0.45 4.17 0.03 0.76 0.32 4. 24 3.64 2.39 2.55 5.91 5.31 ns 16 ma ?f 0.72 6.70 0.05 1.22 0.51 6.83 5.85 3.85 4.10 9.51 8.54 ns std. 0.60 5.58 0.04 1.02 0.43 5. 68 4.87 3.21 3.42 7.92 7.11 ns ?1 0.51 4.75 0.04 0.86 0.36 4. 83 4.14 2.73 2.90 6.74 6.04 ns ?2 0.45 4.17 0.03 0.76 0.32 4. 24 3.64 2.39 2.55 5.91 5.31 ns note: for specific junction temperature and voltage-supply levels, refer to table 3-6 on page 3-4 for derating values. table 3-27 3.3 v lvttl / 3.3 v lvcmos high slew commercial-case conditions: t j = 70c, worst case v cc = 1.425 v, worst case v cci = 3.0 v drive strength (ma) speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 4 ma ?f 0.72 9.20 0.05 1.22 0.51 9. 37 7.91 3.18 3.14 12.05 10.60 ns std. 0.60 7.66 0.04 1.02 0.43 7. 80 6.59 2.65 2.61 10.03 8.82 ns ?1 0.51 6.51 0.04 0.86 0.36 6. 63 5.60 2.25 2.22 8.54 7.51 ns ?2 0.45 5.72 0.03 0.76 0.32 5. 82 4.92 1.98 1.95 7.49 6.59 ns 8 ma ?f 0.72 5.89 0.05 1.22 0.51 6.00 4.89 3.59 3.85 8.69 7.57 ns std. 0.60 4.91 0.04 1.02 0.43 5. 00 4.07 2.98 3.20 7.23 6.30 ns ?1 0.51 4.17 0.04 0.86 0.36 4. 25 3.46 2.54 2.73 6.15 5.36 ns ?2 0.45 3.66 0.03 0.76 0.32 3. 73 3.04 2.23 2.39 5.40 4.71 ns 12 ma ?f 0.72 4.24 0.05 1.22 0.51 4.32 3.39 3.86 4.30 7.01 6.08 ns std. 0.60 3.53 0.04 1.02 0.43 3.60 2.82 3.21 3.58 5.83 5.06 ns ?1 0.51 3.00 0.04 0.86 0.36 3.06 2.40 2.73 3.05 4.96 4.30 ns ?2 0.45 2.64 0.03 0.76 0.32 2.69 2.11 2.40 2.67 4.36 3.78 ns 16 ma ?f 0.72 4.24 0.05 1.22 0.51 4.32 3.39 3.86 4.30 7.01 6.08 ns std. 0.60 3.53 0.04 1.02 0.43 3. 60 2.82 3.21 3.58 5.83 5.06 ns ?1 0.51 3.00 0.04 0.86 0.36 3. 06 2.40 2.73 3.05 4.96 4.30 ns ?2 0.45 2.64 0.03 0.76 0.32 2. 69 2.11 2.40 2.67 4.36 3.78 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage-supply levels, refer to table 3-6 on page 3-4 for derating values.
proasic3 flash family fpgas 3-20 advanced v0.2 2.5 v lvcmos low-voltage cmos for 2.5 v is an ex tension of the lvcmos standard (jesd8-5) used for general purpose 2.5 v applications. it uses a 5-v- tolerant input buffer and push-pull output buffer. table 3-28 minimum and maximum dc input and output levels 2.5 v lvcmos v il v ih v ol v oh i ol i oh i osl i osh i il i ih drive strength min, v max, v min, v max, v max, v min, v ma ma max, ma 1 max, ma 1 a 2 a 2 4 ma ?0.3 0.7 1.7 3.6 0.7 1.7 4 4 18 16 10 10 8 ma ?0.3 0.7 1.7 3.6 0.7 1.7 8 8 37 32 10 10 12 ma ?0.3 0.7 1.7 3.6 0.7 1.7 12 12 74 65 10 10 notes: 1. currents are measured at high temperature (100c junction temperature) and maximum voltage. 2. currents are measured at 85c junction temperature. 3. software default selection highlighted in gray. figure 3-7 ac loading table 3-29 ac waveforms, measuring poin ts and capacitive loads input low (v) input high (v) measuring point* (v) c load (pf) 02.51.235 note: *measuring point = v trip. see table 3-15 on page 3-14 for a complete table of trip points. test point test point enable path data path r to v for t /t /t cci lz zl zls 35 pf for t /t /t /t zh zhs zls zl 5 pf for t /t hz lz r to gnd for t /t /t hz zh zhs 35 pf r = 1 k
proasic3 flash family fpgas advanced v0.2 3-21 timing characteristics table 3-30 2.5 v lvcmos low slew commercial-case conditions: t j = 70c, worst case v cc = 1.425 v, worst case v cci = 2.3 v drive strength (ma) speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 4 ma ?f 0.72 13.69 0.05 1.57 0.51 13.47 13.69 3.22 2.65 16.16 16.38 ns std. 0.60 11.40 0.04 1.31 0.43 11.22 11.40 2.68 2.20 13.45 13.63 ns ?1 0.51 9.69 0.04 1.11 0.36 9.54 9.69 2.28 1.88 11.44 11.60 ns ?2 0.45 8.51 0.03 0.98 0.32 8.38 8.51 2.00 1.65 10.05 10.18 ns 8 ma ?f 0.72 9.56 0.05 1.57 0.51 9. 74 9.39 3.66 3.47 12.43 12.07 ns std. 0.60 7.96 0.04 1.31 0.43 8. 11 7.81 3.05 2.89 10.34 10.05 ns ?1 0.51 6.77 0.04 1.11 0.36 6. 90 6.65 2.59 2.46 8.80 8.55 ns ?2 0.45 5.94 0.03 0.98 0.32 6. 05 5.83 2.28 2.16 7.72 7.50 ns 12 ma ?f 0.72 7.42 0.05 1.57 0.51 7. 56 7.11 3.97 3.99 10.25 9.79 ns std. 0.60 6.18 0.04 1.31 0.43 6. 29 5.92 3.30 3.32 8.53 8.15 ns ?1 0.51 5.26 0.04 1.11 0.36 5. 35 5.03 2.81 2.83 7.25 6.94 ns ?2 0.45 4.61 0.03 0.98 0.32 4. 70 4.42 2.47 2.48 6.37 6.09 ns note: for specific junction temperature and voltage-supply levels, refer to table 3-6 on page 3-4 for derating values. table 3-31 2.5 v lvcmos high slew commercial-case conditions: t j = 70c, worst case v cc = 1.425 v, worst case v cci = 2.3 v drive strength (ma) speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 4 ma ?f 0.72 10.41 0.05 1.57 0.51 9.41 10.41 3.21 2.77 12.09 13.09 ns std. 0.60 8.66 0.04 1.31 0.43 7. 83 8.66 2.68 2.30 10.07 10.90 ns ?1 0.51 7.37 0.04 1.11 0.36 6. 66 7.37 2.28 1.96 8.56 9.27 ns ?2 0.45 6.47 0.03 0.98 0.32 5. 85 6.47 2.00 1.72 7.52 8.14 ns 8 ma ?f 0.72 6.21 0.05 1.57 0.51 6.05 6.21 3.66 3.60 8.73 8.89 ns std. 0.60 5.17 0.04 1.31 0.43 5. 04 5.17 3.05 3.00 7.27 7.40 ns ?1 0.51 4.39 0.04 1.11 0.36 4. 28 4.39 2.59 2.55 6.19 6.30 ns ?2 0.45 3.86 0.03 0.98 0.32 3. 76 3.86 2.28 2.24 5.43 5.53 ns 12 ma ?f 0.72 4.28 0.05 1.57 0.51 4.36 4.12 3.97 4.13 7.04 6.81 ns std. 0.60 3.56 0.04 1.31 0.43 3.62 3.43 3.30 3.44 5.86 5.67 ns ?1 0.51 3.03 0.04 1.11 0.36 3.08 2.92 2.81 2.92 4.99 4.82 ns ?2 0.45 2.66 0.03 0.98 0.32 2.71 2.56 2.47 2.57 4.38 4.23 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage-supply levels, refer to table 3-6 on page 3-4 for derating values.
proasic3 flash family fpgas 3-22 advanced v0.2 1.8 v lvcmos low-voltage cmos for 1.8 v is an extension of the lvcm os standard (jesd8-5) used for general purpose 1.8 v applications. it uses 1.8 v input buf fer and push-pull output buffer. table 3-32 minimum and maximum dc input and output levels 1.8 v lvcmos v il v ih v ol v oh i ol i oh i osl i osh i il i ih drive strength min, v max, v min, v max, vmax, vmin, v mama max, ma 1 max, ma 1 a 2 a 2 2 ma ?0.3 0.35 * v cci 0.65 * v cci 3.6 0.45 v cci ? 0.45 2 2 11 9 10 10 4 ma ?0.3 0.35 * v cci 0.65 * v cci 3.6 0.45 v cci ? 0.45 4 4 22 17 10 10 8 ma ?0.3 0.35 * v cci 0.65 * v cci 3.6 0.45 v cci ? 0.45 8 8 44 35 10 10 notes: 1. currents are measured at high temperature (100c junction temperature) and maximum voltage. 2. currents are measured at 85c junction temperature. 3. software default selection highlighted in gray. figure 3-8 ac loading table 3-33 ac waveforms, measuring poin ts and capacitive loads input low (v) input high (v) measuring point* (v) c load (pf) 01.80.935 note: *measuring point = v trip. see table 3-15 on page 3-14 for a complete table of trip points. test point test point enable path data path r to v for t /t /t cci lz zl zls 35 pf for t /t /t /t zh zhs zls zl 5 pf for t /t hz lz r to gnd for t /t /t hz zh zhs 35 pf r = 1 k
proasic3 flash family fpgas advanced v0.2 3-23 timing characteristics table 3-34 1.8 v lvcmos low slew commercial-case conditions: t j = 70c, worst case v cc = 1.425 v, worst case v cci = 1.7 v drive strength (ma) speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 ma ?f 0.72 14.25 0.05 1.46 0.51 1 0.97 14.25 3.33 1.99 13.66 16.94 ns std. 0.60 11.86 0.04 1.22 0.43 9.1 3 11.86 2.77 1.66 11.37 14.10 ns ?1 0.51 10.09 0.04 1.03 0.36 7.7 7 10.09 2.36 1.41 9.67 11.99 ns ?2 0.45 8.86 0.03 0.91 0.32 6. 82 8.86 2.07 1.24 8.49 10.53 ns 4 ma ?f 0.72 8.31 0.05 1.46 0.51 7.04 8.31 3.87 3.41 9.73 10.99 ns std. 0.60 6.91 0.04 1.22 0.43 5. 86 6.91 3.22 2.84 8.10 9.15 ns ?1 0.51 5.88 0.04 1.03 0.36 4. 99 5.88 2.74 2.41 6.89 7.78 ns ?2 0.45 5.16 0.03 0.91 0.32 4. 38 5.16 2.40 2.12 6.05 6.83 ns 6 ma ?f 0.72 5.34 0.05 1.46 0.51 5.02 5.34 4.24 4.06 7.71 8.03 ns std. 0.60 4.45 0.04 1.22 0.43 4. 18 4.45 3.53 3.38 6.42 6.68 ns ?1 0.51 3.78 0.04 1.03 0.36 3. 56 3.78 3.00 2.88 5.46 5.68 ns ?2 0.45 3.32 0.03 0.91 0.32 3. 12 3.32 2.63 2.52 4.79 4.99 ns 8ma ?f 0.72 14.25 0.05 1.46 0.51 10 .97 14.25 3.33 1.99 13.66 16.94 ns std. 0.60 11.86 0.04 1.22 0.43 9.1 3 11.86 2.77 1.66 11.37 14.10 ns ?1 0.51 10.09 0.04 1.03 0.36 7.7 7 10.09 2.36 1.41 9.67 11.99 ns ?2 0.45 8.86 0.03 0.91 0.32 6. 82 8.86 2.07 1.24 8.49 10.53 ns note: for specific junction temperature and voltage-supply levels, refer to table 3-6 on page 3-4 for derating values. table 3-35 1.8 v lvcmos high slew commercial-case conditions: t j = 70c, worst case v cc = 1.425 v, worst case v cci = 1.7 v drive strength (ma) speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 ma ?f 0.72 18.66 0.05 1.46 0.51 16.95 18.66 3.34 1.92 19.64 21.34 ns std. 0.60 15.53 0.04 1.22 0.43 14.11 15.53 2.78 1.60 16.35 17.77 ns ?1 0.51 13.21 0.04 1.03 0.36 12.01 13.21 2.36 1.36 13.91 15.11 ns ?2 0.45 11.60 0.03 0.91 0.32 10.54 11.60 2.07 1.19 12.21 13.27 ns 4 ma ?f 0.72 12.58 0.05 1.46 0.51 12.51 12.58 3.88 3.28 15.19 15.27 ns std. 0.60 10.47 0.04 1.22 0.43 10.41 10.47 3.23 2.73 12.64 12.71 ns ?1 0.51 8.91 0.04 1.03 0.36 8.86 8.91 2.75 2.33 10.76 10.81 ns ?2 0.45 7.82 0.03 0.91 0.32 7.77 7.82 2.41 2.04 9.44 9.49 ns 6 ma ?f 0.72 9.67 0.05 1.46 0.51 9. 85 9.42 4.25 3.93 12.53 12.11 ns std. 0.60 8.05 0.04 1.22 0.43 8. 20 7.84 3.54 3.27 10.43 10.08 ns ?1 0.51 6.85 0.04 1.03 0.36 6.97 6.67 3.01 2.78 8.88 8.57 ns ?2 0.45 6.01 0.03 0.91 0.32 6.12 5.86 2.64 2.44 7.79 7.53 ns 8 ma ?f 0.72 18.66 0.05 1.46 0.51 16.95 18.66 3.34 1.92 19.64 21.34 ns std. 0.60 15.53 0.04 1.22 0.43 14.11 15.53 2.78 1.60 16.35 17.77 ns ?1 0.51 13.21 0.04 1.03 0.36 12.01 13.21 2.36 1.36 13.91 15.11 ns ?2 0.45 11.60 0.03 0.91 0.32 10.54 11.60 2.07 1.19 12.21 13.27 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage-supply levels, refer to table 3-6 on page 3-4 for derating values.
proasic3 flash family fpgas 3-24 advanced v0.2 1.5 v lvcmos (jesd8-11) low-voltage cmos for 1.5 v is an ex tension of the lvcmos standard (jesd8-5) used for general purpose 1.5v applications. it uses 1.5 v input buf fer and push-pull output buffer. table 3-36 minimum and maximum dc input and output levels 1.5 v lvcmos v il v ih v ol v oh i ol i oh i osl i osh i il i ih drive strength min, v max, v min, v max, v max, v min, v ma ma max, ma 1 max, ma 1 a 2 a 2 2 ma ?0.3 0.30 * v cci 0.7 * v cci 3.6 0.25 * v cci 0.75 * v cci 2 2 16 13 10 10 4 ma ?0.3 0.30 * v cci 0.7 * v cci 3.6 0.25 * v cci 0.75 * v cci 4 4 33 25 10 10 notes: 1. currents are measured at high temperature (100c junction temperature) and maximum voltage. 2. currents are measured at 85c junction temperature. 3. software default selection highlighted in gray. figure 3-9 ac loading table 3-37 ac waveforms, measuring poin ts and capacitive loads input low (v) input high (v) measuring point* (v) c load (pf) 0 1.5 0.75 35 note: *measuring point = v trip. see table 3-15 on page 3-14 for a complete table of trip points. test point test point enable path data path r to v for t /t /t cci lz zl zls 35 pf for t /t /t /t zh zhs zls zl 5 pf for t /t hz lz r to gnd for t /t /t hz zh zhs 35 pf r = 1 k
proasic3 flash family fpgas advanced v0.2 3-25 timing characteristics table 3-38 1.5 v lvcmos low slew commercial-case conditions: t j = 70c, worst case v cc = 1.425 v, worst case v cci = 1.4 v drive strength (ma) speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 ma ?f 0.72 15.36 0.05 1.73 0.51 15.39 15.36 4.08 3.18 18.07 18.04 ns std. 0.60 12.78 0.04 1.44 0.43 12.81 12.78 3.40 2.64 15.04 15.02 ns ?1 0.51 10.87 0.04 1.22 0.36 10.90 10.87 2.89 2.25 12.80 12.78 ns ?2 0.45 9.55 0.03 1.07 0.32 9.56 9.55 2.54 1.97 11.23 11.21 ns 4 ma ?f 0.72 12.02 0.05 1.73 0.51 12.25 11.47 4.50 3.93 14.93 14.15 ns std. 0.60 10.01 0.04 1.44 0.43 10.19 9.55 3.75 3.27 12.43 11.78 ns ?1 0.51 8.51 0.04 1.22 0.36 8.67 8.12 3.19 2.78 10.57 10.02 ns ?2 0.45 7.47 0.03 1.07 0.32 7. 61 7.13 2.80 2.44 9.28 8.80 ns note: for specific junction temperature and voltage-supply levels, refer to table 3-6 on page 3-4 for derating values. table 3-39 1.5 v lvcmos high slew commercial-case conditions: t j = 70c, worst case v cc = 1.425 v, worst case v cci = 1.4 v drive strength (ma) speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 ma ?f 0.72 10.04 0.05 1.73 0.51 8.20 10.04 4.07 3.32 10.88 12.73 ns std. 0.60 8.36 0.04 1.44 0.43 6. 82 8.36 3.39 2.77 9.06 10.60 ns ?1 0.51 7.11 0.04 1.22 0.36 5.80 7.11 2.88 2.35 7.71 9.02 ns ?2 0.45 6.24 0.03 1.07 0.32 5.09 6.24 2.53 2.06 6.76 7.91 ns 4 ma ?f 0.72 6.38 0.05 1.73 0.51 5.83 6.38 4.49 4.09 8.51 9.07 ns std. 0.60 5.31 0.04 1.44 0.43 4.85 5.31 3.74 3.40 7.09 7.55 ns ?1 0.51 4.52 0.04 1.22 0.36 4.12 4.52 3.18 2.89 6.03 6.42 ns ?2 0.45 3.97 0.03 1.07 0.32 3.62 3.97 2.79 2.54 5.29 5.64 ns notes: 1. software default selection highlighted in gray. 2. for specific junction temperature and voltage-supply levels, refer to table 3-6 on page 3-4 for derating values.
proasic3 flash family fpgas 3-26 advanced v0.2 3.3 v pci, 3.3 v pci-x peripheral component interfac e for 3.3 v standard specifies support fo r 33 mhz and 66 mhz pci bus applications. ac loadings are defined per the pci/p ci-x specifications for the data pa th; actel loadings for enable path characterization are described in figure 3-10 . ac loading are defined per pci/pci-x sp ecifications for the data path; actel loading for tristate is described in table 3-41 . timing characteristics table 3-40 minimum and maximum dc input and output levels 3.3 v pci/pci-x v il v ih v ol v oh i ol i oh i osl i osh i il i ih drive strength min, v max, v min, v max, v max, v min, v ma ma max, ma 1 max, ma 1 a 2 a 2 per pci specification per pci curves 10 10 notes: 1. currents are measured at high temperature (100c junction temperature) and maximum voltage. 2. currents are measured at 85c junction temperature. figure 3-10 ac loading table 3-41 ac waveforms, measuring poin ts and capacitive loads input low (v) input high (v) measuring point* (v) c load (pf) 0 3.3 0.285 * v cci for t dp(r) 0.615 * v cci for t dp(f) 10 note: *measuring point = v trip. see table 3-15 on page 3-14 for a complete table of trip points. table 3-42 3.3 v pci/pci-x commercial-case conditions: t j = 70c, worst case v cc = 1.425 v, worst case v cci = 3.0 v speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units ?f 0.72 3.22 0.05 1.04 0.51 3. 28 2.34 3.86 4.3 3.28 2.34 ns std. 0.60 2.68 0.04 0.86 0.43 2. 73 1.95 3.21 3.58 2.73 1.95 ns ?1 0.51 2.28 0.04 0.73 0.36 2. 32 1.66 2.73 3.05 2.32 1.66 ns ?2 0.45 2.00 0.03 0.65 0.32 2. 04 1.46 2.40 2.67 2.04 1.46 ns note: for specific junction temperature and voltage-supply levels, refer to table 3-6 on page 3-4 for derating values. test point enable path r to v for t /t /t cci lz zl zls 10 pf for t /t /t /t zh zhs zls zl 5 pf for t hz /t lz r to gnd for t /t /t hz zh zhs r = 1 k test point data path r = 25 r to v cci for t dp (f) r to gnd for t dp (r)
proasic3 flash family fpgas advanced v0.2 3-27 differential i/o characteristics physical implementation configuration of th e i/o modules as a differential pair is handled by actel designer software when the user instantiates a differential i/o macro in the design. differential i/os can also be used in conjunction with the embedded input register (inreg), output register (outreg), enable register (enreg), and double data rate (ddr). however, there is no support for bidirectional i/os or tristates with these standards. lvds low-voltage differential sign al (ansi/tia/eia-644) is a high-speed, differential i/o stan dard. it requires that one data bit is carried through two signal lines, so two pins are needed. it also requires external resistor termination. the full implementation of the lvds transmitter and receiver is shown in an example in figure 3-11 . the building blocks of the lvds transmitter-receiver are one transmitter macro, one receiver macro, three board resistors at the transmitter end, and one resistor at the receiver end. the values for the three driver resistors are different from those used in the lvpecl implementation, because the output standard specifications are different. figure 3-11 lvds circuit diag ram and board-leve l implementation table 3-43 minimum and maximum dc input and output levels dc parameter description min. typ. max. units v cci supply voltage 2.375 2.5 2.625 v v ol output low voltage 0.9 1.075 1.25 v v oh output high voltage 1.25 1.425 1.6 v v i input voltage 0 2.925 v v odiff differential output voltage 250 350 450 mv v ocm output common mode voltage 1.125 1.25 1.375 v v icm input common mode voltage 0.05 1.25 2.35 v v idiff input differential voltage 100 350 mv notes: 1. 5% 2. differential input voltage = 350 mv. table 3-44 ac waveforms, measuring poin ts and capacitive loads input low (v) input high (v) measuring point* (v) 1.075 1.325 cross point note: *measuring point = v trip. see table 3-15 on page 3-14 for a complete table of trip points. 140 ? 100 ? zo = 50 ? zo = 50 ? 165 ? 165 ? + - p n p n inbuf_lvds outbuf_lvds fpga fpga bourns part number: cat16-lv4f12
proasic3 flash family fpgas 3-28 advanced v0.2 timing characteristics table 3-45 lvds commercial-case conditions: t j = 70c, worst case v cc = 1.425 v, worst case v cci = 2.3 v speed grade t dout t dp t din t py units ?f 0.72 2.2 0.05 1.92 ns std. 0.60 1.83 0.04 1.60 ns ?1 0.51 1.55 0.04 1.36 ns ?2 0.45 1.36 0.03 1.20 ns note: for specific junction temperature and voltage-supply levels, refer to table 3-6 on page 3-4 for derating values.
proasic3 flash family fpgas advanced v0.2 3-29 lvpecl low-voltage positive emitter-coupled logic (lvpecl) is another differential i/o standa rd. it requires that one data bit is carried through two signal lines. like lvds, two pins are needed. it also requires external resistor termination. the full implementation of the lvds transmitter and receiver is shown in an example in figure 3-12 . the building blocks of the lvpec l transmitter-receiver are one transmitter macro, one re ceiver macro, three board resistors at the transmitter end, and one resistor at the receiver end. the values for the three driver resistors are different from those used in the lvds implementation, because the output standard spec ifications are different. timing characteristics figure 3-12 lvpecl circuit diagram and board-level implementation table 3-46 minimum and maximum dc input and output levels dc parameter description min. max. min. max. min. max. units v cci supply voltage 3.0 3.3 3.6 v v ol output low voltage 0.96 1.27 1.06 1.43 1.30 1.57 v v oh output high voltage 1.8 2.11 1.92 2.28 2.13 2.41 v v il , v ih input low, input high voltages 0 3.3 0 3.6 0 3.9 v v odiff differential output voltage 0.625 0.97 0.625 0.97 0.625 0.97 v v ocm output common mode voltage 1.762 1.98 1.762 1.98 1.762 1.98 v v icm input common mode voltage 1.01 2.57 1.01 2.57 1.01 2.57 v v idiff input differential voltage 300 300 300 mv table 3-47 ac waveforms, measuring poin ts and capacitive loads input low (v) input high (v) measuring point* (v) 1.64 1.94 cross point note: *measuring point = v trip. see table 3-15 on page 3-14 for a complete table of trip points. table 3-48 lvpecl commercial-case conditions: t j = 70c, worst case v cc = 1.425 v, worst case v cci = 3.0 v speed grade t dout t dp t din t py units ?f 0.72 2.16 0.05 1.69 ns std. 0.60 1.80 0.04 1.40 ns ?1 0.51 1.53 0.04 1.19 ns ?2 0.45 1.34 0.03 1.05 ns note: for specific junction temperature and voltage-supply levels, refer to table 3-6 on page 3-4 for derating values. 187 w 100 ? zo = 50 ? zo = 50 ? 100 ? 100 ? + - p n p n inbuf_lvpecl outbuf_lvpecl fpga fpga bourns part number: cat16-pc4f12
proasic3 flash family fpgas 3-30 advanced v0.2 i/o register specifications fully registered i/o buffers with synchro nous enable and asynchronous preset figure 3-13 timing model of registered i/o buffers with synchronous enable and asynchronous preset inbuf inbuf inbuf tribuf clkbuf inbuf inbuf clkbuf data input i/o register with: active high enable active high preset postive edge triggered data output register and enable output register with: active high enable active high preset postive edge triggered pad out clk enable preset data_out data x x x x x x x x x x x x x x x eout dout enable clk dq dfn1e1p1 pre dq dfn1e1p1 pre dq dfn1e1p1 pre d_enable a b c d e e e e f g h i j l k y core array
proasic3 flash family fpgas advanced v0.2 3-31 table 3-49 parameter definition and measuring nodes parameter name parameter definition measuring nodes (from, to)* t oclkq clock-to-q of the output data register h, dout t osud data setup time for the output data register f, h t ohd data hold time for the output data register f, h t osue enable setup time for the output data register g, h t ohe enable hold time for the output data register g, h t opre2q asynchronous preset-to-q of th e output data register l, dout t orempre asynchronous preset removal time for the output data register l, h t orecpre asynchronous preset recovery time for the output data register l, h t oeclkq clock-to-q of the output enable register h, eout t oesud data setup time for the output enable register j, h t oehd data hold time for the output enable register j, h t oesue enable setup time for the ou tput enable register k, h t oehe enable hold time for the ou tput enable register k, h t oepre2q asynchronous preset-to-q of the output enable register i, eout t oerempre asynchronous preset removal time fo r the output enable register i, h t oerecpre asynchronous preset recovery time for the output enable register i, h t iclkq clock-to-q of the input data register a, e t isud data setup time for the input data register c, a t ihd data hold time for the input data register c, a t isue enable setup time for the input data register b, a t ihe enable hold time for the input data register b, a t ipre2q asynchronous preset-to-q of the input data register d, e t irempre asynchronous preset removal time for the input data register d, a t irecpre asynchronous preset recovery time for the input data register d, a note: *see figure 3-13 on page 3-30 for more information.
proasic3 flash family fpgas 3-32 advanced v0.2 fully registered i/o buffers with synchr onous enable and asynchronous clear figure 3-14 timing model of the registered i/o buffers wi th synchronous enable and asynchronous clear enable clk pad out clk enable clr data_out data y x x x x x x x x aa x x x x x eout dout core array dq dfn1e1c1 e clr dq dfn1e1c1 e clr dq dfn1e1c1 e clr d_enable data input i/o register with active high enable active high clear positive edge triggered data output register and enable output register with active high enable active high clear positive edge triggered bb cc dd ee ff gg ll hh jj kk clkbuf inbuf inbuf tribuf inbuf inbuf clkbuf inbuf
proasic3 flash family fpgas advanced v0.2 3-33 table 3-50 parameter definition and measuring nodes parameter name parameter definition measuring nodes (from, to)* toc lk q clock-to-q of the output data register hh, dout t osud data setup time for the output data register ff, hh t ohd data hold time for the output data register ff, hh t osue enable setup time for the output data register gg, hh t ohe enable hold time for the output data register gg, hh t oclr2q asynchronous clear-to-q of the output data register ll, dout t oremclr asynchronous clear removal time for the output data register ll, hh t orecclr asynchronous clear recovery time for the output data register ll, hh t oeclkq clock-to-q of the output enable register hh, eout t oesud data setup time for the output enable register jj, hh t oehd data hold time for the output enable register jj, hh t oesue enable setup time for the ou tput enable register kk, hh t oehe enable hold time for the output enable register kk, hh t oeclr2q asynchronous clear-to-q of the output enable register ii, eout t oeremclr asynchronous clear removal time for the output enable register ii, hh t oerecclr asynchronous clear recovery time for the output enable register ii, hh t iclkq clock-to-q of the input data register aa, ee t isud data setup time for the input data register cc, aa t ihd data hold time for the input data register cc, aa t isue enable setup time for the input data register bb, aa t ihe enable hold time for the input data register bb, aa t iclr2q asynchronous clear-to-q of the input data register dd, ee t iremclr asynchronous clear removal time for the input data register dd, aa t irecclr asynchronous clear recovery time for the input data register dd, aa note: *see figure 3-14 on page 3-32 for more information.
proasic3 flash family fpgas 3-34 advanced v0.2 input register timing characteristics figure 3-15 input register timing diagram 50% preset clear out_1 clk data enable t isue 50% 50% t isud t ihd 50% 50% t iclkq 1 0 t ihe t irecpre t irempre t irecclr t iremclr t iwclr t iwpre t ipre2q t iclr2q t ickmpwh t ickmpwl 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% table 3-51 input data register propagation delays commercial-case conditions: t j = 70c, worst case v cc = 1.425 v parameter description ?2 ?1 std. ?f units t iclkq clock-to-q of the input data register 0.63 0.71 0.84 1.01 ns t isud data setup time for the input data register 0.43 0.49 0.57 0.69 ns t ihd data hold time for the input data register 0.00 0.00 0.00 0.00 ns t isue enable setup time for the input data register 0.43 0.49 0.57 0.69 ns t ihe enable hold time for the input data register 0.00 0.00 0.00 0.00 ns t iclr2q asynchronous clear-to-q of the input data register 0.57 0.65 0.76 1.01 ns t ipre2q asynchronous preset-to-q of the input data register 0.45 0.51 0.60 0.72 ns t iremclr asynchronous clear removal time for the input data register 0.00 0.00 0.00 0.00 ns t irecclr asynchronous clear recovery time for th e input data register 0.10 0.10 0.10 0.10 ns t irempre asynchronous preset removal time for the input data register 0.00 0.00 0.00 0.00 ns t irecpre asynchronous preset recovery time for the input data register 0.10 0.10 0.10 0.10 ns t iwclr asynchronous clear minimum pulse width for the input data register 0.25 0.28 0.33 0.40 ns t iwpre asynchronous preset minimum pulse width for the input data register 0.25 0.28 0.33 0.40 ns t ickmpwh clock minimum pulse width high for the input data register 0.36 0.41 0.48 0.58 ns t ickmpwl clock minimum pulse width low for the input data register 0.41 0.46 0.54 0.65 ns note: for specific junction temperature and voltage-supply levels, refer to table 3-6 on page 3-4 for derating values.
proasic3 flash family fpgas advanced v0.2 3-35 output register timing characteristics figure 3-16 output register timing diagram preset clear dout clk data_out enable t osue 50% 50% t osud t ohd 50% 50% t oclkq 1 0 t ohe t orecpre t orempre t orecclr t oremclr t owclr t owpre t opre2q t oclr2q t ockmpwh t ockmpwl 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% table 3-52 output data register propagation delays commercial-case conditions: t j = 70c, worst case v cc = 1.425 v parameter description ?2 ?1 std. ?f units t oclkq clock-to-q of the output data register 0.63 0.71 0.84 1.01 ns t osud data setup time for the output data register 0.43 0.49 0.57 0.69 ns t ohd data hold time for the output data register 0.00 0.00 0.00 0.00 ns t osue enable setup time for the output data register 0.43 0.49 0.57 0.69 ns t ohe enable hold time for the output data register 0.00 0.00 0.00 0.00 ns t oclr2q asynchronous clear-to-q of the out put data register 0.57 0.65 0.76 1.01 ns t opre2q asynchronous preset-to-q of the output data register 0.45 0.51 0.60 0.72 ns t oremclr asynchronous clear removal time for the output data register 0.00 0.00 0.00 0.00 ns t orecclr asynchronous clear recovery time for the output data register 0.24 0.27 0.32 0.38 ns t orempre asynchronous preset removal time for the output data register 0.00 0.00 0.00 0.00 ns t orecpre asynchronous preset recovery time for th e output data register 0.24 0.27 0.32 0.38 ns t owclr asynchronous clear minimum pulse width for th e output data register 0.26 0.29 0.34 0.41 ns t owpre asynchronous preset minimum pulse width for the output data register 0.26 0.29 0.34 0.41 ns t ockmpwh clock minimum pulse width high for the output data register 0.38 0.43 0.51 0.61 ns t ockmpwl clock minimum pulse width low for the ou tput data register 0.43 0.49 0.57 0.69 ns note: for specific junction temperature and voltage-supply levels, refer to table 3-6 on page 3-4 for derating values.
proasic3 flash family fpgas 3-36 advanced v0.2 output enable register timing characteristics figure 3-17 output enable register timing diagram table 3-53 output enable register propagation delays commercial-case conditions: t j = 70c, worst case v cc = 1.425 v parameter description ?2 ?1 std. ?f units t oeclkq clock-to-q of the output enable register 0.63 0.71 0.84 1.01 ns t oesud data setup time for the output enable register 0.43 0.49 0.57 0.69 ns t oehd data hold time for the output enable register 0.00 0.00 0.00 0.00 ns t oesue enable setup time for the output enable register 0.43 0.49 0.57 0.69 ns t oehe enable hold time for the output enable register 0.00 0.00 0.00 0.00 ns t oeclr2q asynchronous clear-to-q of the output enable register 0.57 0.65 0.76 1.01 ns t oepre2q asynchronous preset-to-q of the output enable register 0.45 0.51 0.60 0.72 ns t oeremclr asynchronous clear removal time for the ou tput enable register 0.00 0.00 0.00 0.00 ns t oerecclr asynchronous clear recovery time for the output enable register 0.24 0.27 0.32 0.38 ns t oerempre asynchronous preset removal time for the output enable register 0.00 0.00 0.00 0.00 ns t oerecpre asynchronous preset recovery time for the output enable register 0.24 0.27 0.32 0.38 ns t oewclr asynchronous clear minimum pulse width for th e output enable register 0.26 0.29 0.34 0.41 ns t oewpre asynchronous preset minimum pulse width for the output enable register 0.26 0.29 0.34 0.41 ns t oeckmpwh clock minimum pulse width high for the output enable register 0.38 0.43 0.51 0.61 ns t oeckmpwl clock minimum pulse width low for the ou tput enable register 0.43 0.49 0.57 0.69 ns note: for specific junction temperature and voltage-supply levels, refer to table 3-6 on page 3-4 for derating values. 50% preset clear eout clk d_enable enable t oesue 50% 50% t oesud t oehd 50% 50% t oeclkq 1 0 t oehe t oerecpre t oerempre t oerecclr t oeremclr t oewclr t oewpre t oepre2q t oeclr2q t oeckmpwh t oeckmpwl 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50%
proasic3 flash family fpgas advanced v0.2 3-37 ddr module specifications input ddr module figure 3-18 input ddr timing model table 3-54 parameter definitions parameter name parameter definiti on measuring nodes (from, to) t ddriclkq1 clock-to-out out_qr b, d t ddriclkq2 clock-to-out out_qf b, e t ddrisud data setup time of ddr input a, b t ddrihd data hold time of ddr input a, b t ddriclr2q1 clear-to-out out_qr c, d t ddriclr2q2 clear-to-out out_qf c, e t ddriremclr clear removal c, b t ddrirecclr clear recovery c, b input ddr data clk clkbuf inbuf out_qf (to core) ff2 ff1 inbuf clr ddr_in x x x x x e a b c d out_qr (to core)
proasic3 flash family fpgas 3-38 advanced v0.2 timing characteristics table 3-55 input ddr timing diagram ddriclkq2 t ddriclr2q2 t ddriremclr t ddrirecclr t ddriclr2q1 12 3 4 5 6 7 8 9 clk data clr out_qr out_qf t ddriclkq1 2 4 6 3 5 7 t ddrihd t ddrisud t table 3-56 input ddr propagation delays commercial-case conditions: t j = 70c, worst case v cc = 1.425 v parameter description ?2 ?1 std. ?f units t ddriclkq1 clock-to-out out_qr for input ddr 0.63 0.71 0.84 1.01 ns t ddriclkq2 clock-to-out out_qf for input ddr 0.63 0.71 0.84 0.91 ns t ddrisud data setup for input ddr 0.43 0.49 0.57 0.86 ns t ddrihd data hold for input ddr 0.00 0.00 0.00 0.00 ns t ddriclr2q1 asynchronous clear to out out_qr for input ddr 0.57 0.65 0.76 0.91 ns t ddriclr2q2 asynchronous clear to out out_qf for input ddr 0.57 0.65 0.76 0.91 ns t ddriremclr asynchronous clear removal time for input ddr 0.00 0.00 0.00 0.00 ns t ddrirecclr asynchronous clear recovery time for input ddr 0.10 0.10 0.10 0.10 ns t ddriwclr asynchronous clear minimum pulse width for input ddr ns t ddrickmpwh clock minimum pulse width high for input ddr ns t ddrickmpwl clock minimum pulse widt h low for input ddr ns f ddrimax maximum frequency for input ddr mhz note: for specific junction temperature and voltage-supply levels, refer to table 3-6 on page 3-4 for derating values.
proasic3 flash family fpgas advanced v0.2 3-39 output ddr module figure 3-19 output ddr timing model table 3-57 parameter definitions parameter name parameter definition measuring nodes (from, to) t ddroclkq clock-to-out b, e t ddroclr2q asynchronous clear-to-out c, e t ddroremclr clear removal c, b tddr orecclr clear recovery c, b tddr os ud1 data setup data_f a, b t ddrosud2 data setup data_r d, b t ddrohd1 data hold data_f a, b t ddrohd2 data hold data_r d, b data_f (from core) clk clkbuf out ff2 inbuf clr ddr_out ff1 0 1 x x x x x x x a b d e c c b outbuf data_r (from core)
proasic3 flash family fpgas 3-40 advanced v0.2 timing characteristics figure 3-20 output ddr timing diagram 11 6 1 7 2 8 3 910 45 28 3 9 t ddroremclr t ddrohd1 t ddrosud1 t ddrohd2 t ddrosud2 t ddroclkq t ddrorecclr clk data_r data_f clr out t ddroclr2q 710 4 table 3-58 output ddr propagation delays commercial-case conditions: t j = 70c, worst case v cc = 1.425 v parameter description ?2 ?1 std. ?f units t ddroclkq clock-to-out of ddr for output ddr 0.63 0.71 0.84 1.01 ns t ddrosud1 data_f data setup for output ddr 0.43 0.49 0.57 0.69 ns t ddrosud2 data_r data setup for out put ddr 0.43 0.49 0.57 0.69 ns t ddrohd1 data_f data hold for output ddr 0.00 0.00 0.00 0.00 ns t ddrohd2 data_r data hold for output ddr 0.00 0.00 0.00 0.00 ns t ddroclr2q asynchronous clear to out for output ddr 0.57 0.65 0.76 0.91 ns t ddroremclr asynchronous clear removal time for output ddr 0.00 0.00 0.00 0.00 ns t ddrorecclr asynchronous clear recovery time for output ddr 0.10 0.10 0.10 0.10 ns t ddrowclr1 asynchronous clear minimum pulse width for output ddr ns t ddrockmpwh clock minimum pulse width high for the output ddr ns t ddrockmpwl clock minimum pulse width low for the output ddr ns f ddomax maximum frequency fo r the output ddr mhz note: for specific junction temperature and voltage-supply levels, refer to table 3-6 on page 3-4 for derating values.
proasic3 flash family fpgas advanced v0.2 3-41 versatile characteristics versatile specifications as a combinatorial module the proasic3 library offers all combinati ons of lut-3 combinatorial functions. in this section, timing characteristics are presented for a sample of the library. for more details, refer to the proasic3/e macro library guide . figure 3-21 sample of combinatorial cells maj3 a c by mux2 b 0 1 a s y ay b b a xor2 y nor2 b a y b a y or2 inv a y and2 b a y nand3 b a c xor3 y b a c nand2
proasic3 flash family fpgas 3-42 advanced v0.2 figure 3-22 timing model and waveforms nand2 or any combinatorial logic a b y t pd t pd (rr) a, b, c out 50% gnd t pd (ff) 50% 50% 50% v cca v cca gnd t pd (rf) 50% t = max(t , t ), t , t ) where edges are applicable for the particular combinatorial cell t pd (fr) 50% v cca out gnd pd pd(rr) pd(rf) pd(ff) pd(fr)
proasic3 flash family fpgas advanced v0.2 3-43 timing characteristics versatile specifications as a sequential module the proasic3 library offers a wide vari ety of sequential cells including flip-f lops and latches. each have a data input and optional enable, clear, or preset. in this section, timi ng characteristics ar e presented for a representative sample from the library. for more details, refer to the proasic3/e macro library guide . table 3-59 combinatorial cell propagation delays commercial-case conditions: t j = 70c, worst case v cc = 1.425 v combinatorial cell equation parameter ?2 ?1 std. ?f units inv y = !a t pd 0.40 0.45 0.53 0.64 ns and2 y = a . b t pd 0.46 0.52 0.62 0.74 ns nand2 y = !(a . b) t pd 0.46 0.52 0.62 0.74 ns or2 y = a + b t pd 0.47 0.54 0.63 0.76 ns nor2 y = !(a + b) t pd 0.47 0.54 0.63 0.76 ns xor2 y = a bt pd 0.72 0.82 0.96 1.15 ns maj3 y = maj (a , b, c) t pd 0.67 0.76 0.90 1.08 ns xor3 y = a b ct pd 0.85 0.97 1.14 1.37 ns mux2 y = a !s + b s t pd 0.49 0.56 0.65 0.79 ns and3 y = a . b . c t pd 0.54 0.62 0.73 0.87 ns note: for specific junction temperature and voltage-supply levels, refer to table 3-6 on page 3-4 for derating values. figure 3-23 sample of sequential cells dq dfn1 data clk out d q dfn1c1 data clk out clr dq dfi1e1p1 data clk out en pre d q dfn1e1 data clk out en
proasic3 flash family fpgas 3-44 advanced v0.2 timing characteristics figure 3-24 timing model and waveforms pre clr out clk data en t sue 50% 50% t sud t hd 50% 50% t clkq 0 t he t recpre t rempre t recclr t remclr t wclr t wpre t pre2q t clr2q t ckmpwh t ckmpwl 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% table 3-60 register delays commercial-case conditions: t j = 70c, worst case v cc = 1.425 v parameter description ?2 ?1 std. ?f units t clkq clock-to-q of the core register 0.54 0.61 0.72 0.86 ns t sud data setup time for the core register 0.40 0.46 0.54 0.65 ns t hd data hold time for the core register 0.00 0.00 0.00 0.00 ns t sue enable setup time for the core register 0.43 0.49 0.57 0.69 ns t he enable hold time for the core register 0.00 0.00 0.00 0.00 ns t clr2q asynchronous clear-to-q of the core register 0.40 0.45 0.53 0.64 ns t pre2q asynchronous preset-to-q of the core register 0.40 0.45 0.53 0.64 ns t remclr asynchronous clear removal time for the core register 0.00 0.00 0.00 0.00 ns t recclr asynchronous clear recovery time for the core register 0.24 0.27 0.32 0.38 ns t rempre asynchronous preset removal time for the core register 0.00 0.00 0.00 0.00 ns t recpre asynchronous preset recovery time for the core register 0.24 0.27 0.32 0.38 ns t wclr asynchronous clear minimum pulse width for the core register 0.26 0.29 0.34 0.41 ns t wpre asynchronous preset minimum pulse width for the core register 0.26 0.29 0.34 0.41 ns t ckmpwh clock minimum pulse width high for the core register 0.38 0.43 0.51 0.61 ns t ckmpwl clock minimum pulse width low for the core register 0.43 0.49 0.57 0.69 ns note: for specific junction temperature and voltage-supply levels, refer to table 3-6 on page 3-4 for derating values.
proasic3 flash family fpgas advanced v0.2 3-45 global resource characteristics a3p250 clock tree topology clock delays are device-specific. figure 3-25 is an example of a global tree used for clock routing. the global tree presented in figure 3-25 is driven by a ccc located on the west side of the a3p250 device. it is used to drive all d-flip- flops in the device. figure 3-25 example of global tree use in an a3p250 device for clock routing central global rib versatile rows global spine ccc
proasic3 flash family fpgas 3-46 advanced v0.2 global tree timing characteristics global clock delays include the central rib delay, the spin e delay, and the row delay. delays do not include i/o input buffer clock delays, as these are i/o stan dard dependent and the clock may be driv en and conditioned internally by the ccc module. for more details on clock conditioning capabilities, refer to "clock conditioning circuits" section on page 2-13 . table 3-61 to table 3-67 on page 3-49 present minimum and maximum global clock delays within each device. minimum and maximum delays are measured with minimum and maximum loading. timing characteristics table 3-61 a3p030 global resource commercial-case conditions: t j = 70c, v cc = 1.425 v parameter description ?2 ?1 std. ?f units min. 1 max. 2 min. 1 max. 2 min. 1 max. 2 min. 1 max. 2 t rckl input low delay for global clock ns t rckh input high delay for global clock ns t rckmpwh minimum pulse width high for global clock ns t rckmpwl minimum pulse width low for global clock ns t rcksw maximum skew for global clock ns f rmax maximum frequency for global clock mhz notes: 1. value reflects minimum load. the delay is measured from the ccc output to the clock pi n of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. value reflects maximum load. the delay is measured on the clock pin of the farthest sequential element, located in a fully lo aded row (all available flip-flops are connec ted to the global net in the row). 3. for specific junction temperature and voltage-supply levels, refer to table 3-6 on page 3-4 for derating values. table 3-62 A3P060 global resource commercial-case conditions: t j = 70c, v cc = 1.425 v parameter description ?2 ?1 std. ?f units min. 1 max. 2 min. 1 max. 2 min. 1 max. 2 min. 1 max. 2 t rckl input low delay for global clock 1.0 5 1.18 1.02 1.34 1.20 1.58 1.44 1.91 ns t rckh input high delay for global clock 1.0 7 1.19 1.02 1.36 1.21 1.60 1.45 1.91 ns t rckmpwh minimum pulse width high for global clock ns t rckmpwl minimum pulse width low for global clock ns t rcksw maximum skew for global cl ock 0.14 0.34 0.40 0.47 ns f rmax maximum frequency for global clock mhz notes: 1. value reflects minimum load. the delay is measured from the ccc output to the clock pi n of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. value reflects maximum load. the delay is measured on the clock pin of the farthest sequential element, located in a fully lo aded row (all available flip-flops are connec ted to the global net in the row). 3. for specific junction temperature and voltage-supply levels, refer to table 3-6 on page 3-4 for derating values.
proasic3 flash family fpgas advanced v0.2 3-47 table 3-63 a3p125 global resource commercial-case conditions: t j = 70c, v cc = 1.425 v parameter description ?2 ?1 std. ?f units min. 1 max. 2 min. 1 max. 2 min. 1 max. 2 min. 1 max. 2 t rckl input low delay for global clock 1.1 0 1.23 1.08 1.40 1.26 1.64 1.52 1.99 ns t rckh input high delay for global clock 1.1 2 1.24 1.07 1.41 1.26 1.66 1.52 1.98 ns t rckmpwh minimum pulse width high for global clock ns t rckmpwl minimum pulse width low for global clock ns t rcksw maximum skew for global cl ock 0.14 0.34 0.40 0.47 ns f rmax maximum frequency for global clock mhz notes: 1. value reflects minimum load. the delay is measured from the ccc output to the clock pi n of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. value reflects maximum load. the delay is measured on the clock pin of the farthest sequential element, located in a fully lo aded row (all available flip-flops are connec ted to the global net in the row). 3. for specific junction temperature and voltage-supply levels, refer to table 3-6 on page 3-4 for derating values. table 3-64 a3p250 global resource commercial-case conditions: t j = 70c, v cc = 1.425v parameter description ?2 ?1 std. ?f units min. 1 max. 2 min. 1 max. 2 min. 1 max. 2 min. 1 max. 2 t rckl input low delay for global clock 1.1 0 1.22 1.07 1.40 1.26 1.64 1.52 1.99 ns t rckh input high delay for global clock 1.1 1 1.24 1.07 1.41 1.26 1.65 1.52 1.98 ns t rckmpwh minimum pulse width high for global clock ns t rckmpwl minimum pulse width low for global clock ns t rcksw maximum skew for global cl ock 0.14 0.34 0.39 0.47 ns f rmax maximum frequency for global clock mhz notes: 1. value reflects minimum load. the delay is measured from the ccc output to the clock pi n of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. value reflects maximum load. the delay is measured on the clock pin of the farthest sequential element, located in a fully lo aded row (all available flip-flops are connec ted to the global net in the row). 3. for specific junction temperature and voltage-supply levels, refer to table 3-6 on page 3-4 for derating values.
proasic3 flash family fpgas 3-48 advanced v0.2 table 3-65 a3p400 global resource commercial-case conditions: t j = 70c, v cc = 1.425 v parameter description ?2 ?1 std. ?f units min. 1 max. 2 min. 1 max. 2 min. 1 max. 2 min. 1 max. 2 t rckl input low delay for global clock 1.1 5 1.27 1.13 1.45 1.33 1.70 1.59 2.06 ns t rckh input high delay for global clock 1.1 6 1.28 1.12 1.46 1.32 1.72 1.59 2.05 ns t rckmpwh minimum pulse width high for global clock ns t rckmpwl minimum pulse width low for global clock ns t rcksw maximum skew for global cl ock 0.13 0.34 0.40 0.47 ns f rmax maximum frequency for global clock mhz notes: 1. value reflects minimum load. the delay is measured from the ccc output to the clock pi n of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. value reflects maximum load. the delay is measured on the clock pin of the farthest sequential element, located in a fully lo aded row (all available flip-flops are connec ted to the global net in the row). 3. for specific junction temperature and voltage-supply levels, refer to table 3-6 on page 3-4 for derating values. table 3-66 a3p600 global resource commercial-case conditions: t j = 70c, v cc = 1.425 v parameter description ?2 ?1 std. ?f units min. 1 max. 2 min. 1 max. 2 min. 1 max. 2 min. 1 max. 2 t rckl input low delay for global clock 1.1 5 1.27 1.13 1.45 1.33 1.70 1.59 2.06 ns t rckh input high delay for global clock 1.1 6 1.28 1.12 1.46 1.32 1.72 1.59 2.05 ns t rckmpwh minimum pulse width high for global clock ns t rckmpwl minimum pulse width low for global clock ns t rcksw maximum skew for global cl ock 0.13 0.34 0.40 0.47 ns f rmax maximum frequency for global clock mhz notes: 1. value reflects minimum load. the delay is measured from the ccc output to the clock pi n of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. value reflects maximum load. the delay is measured on the clock pin of the farthest sequential element, located in a fully lo aded row (all available flip-flops are connec ted to the global net in the row). 3. for specific junction temperature and voltage-supply levels, refer to table 3-6 on page 3-4 for derating values.
proasic3 flash family fpgas advanced v0.2 3-49 table 3-67 a3p1000 global resource commercial-case conditions: t j = 70c, v cc = 1.425 v parameter description ?2 ?1 std. ?f units min. 1 max. 2 min. 1 max. 2 min. 1 max. 2 min. 1 max. 2 t rckl input low delay for global clock 1.1 9 1.32 1.18 1.50 1.39 1.76 1.67 2.13 ns t rckh input high delay for global clock 1.2 0 1.32 1.18 1.51 1.38 1.77 1.66 2.12 ns t rckmpwh minimum pulse width high for global clock ns t rckmpwl minimum pulse width low for global clock ns t rcksw maximum skew for global cl ock 0.13 0.33 0.39 0.47 ns f rmax maximum frequency for global clock mhz notes: 1. value reflects minimum load. the delay is measured from the ccc output to the clock pi n of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. value reflects maximum load. the delay is measured on the clock pin of the farthest sequential element, located in a fully lo aded row (all available flip-flops are connec ted to the global net in the row). 3. for specific junction temperature and voltage-supply levels, refer to table 3-6 on page 3-4 for derating values.
proasic3 flash family fpgas 3-50 advanced v0.2 embedded sram and fifo characteristics sram figure 3-26 ram models addra11 douta8 douta7 douta0 doutb8 doutb7 doutb0 addra10 addra0 dina8 dina7 dina0 widtha1 widtha0 pipea wmodea blka wena clka addrb11 addrb10 addrb0 dinb8 dinb7 dinb0 widthb1 widthb0 pipeb wmodeb blkb wenb clkb ram4k9 raddr8 rd17 raddr7 rd16 raddr0 rd0 wd17 wd16 wd0 ww1 ww0 rw1 rw0 pipe ren rclk ram512x18 waddr8 waddr7 waddr0 wen wclk reset reset
proasic3 flash family fpgas advanced v0.2 3-51 timing waveforms figure 3-27 ram read for flow-through output figure 3-28 ram read for pipelined output clk add blk_b wen_b do a 0 a 1 a 2 d 0 d 1 d 2 t cyc t ckh t ckl t as t ah t bks t ens t enh t doh1 t bkh d n t ckq1 clk add blk_b wen_b do a 0 a 1 a 2 d 0 d 1 t cyc t ckh t ckl t as t ah t bks t ens t enh t doh2 t ckq2 t bkh d n
proasic3 flash family fpgas 3-52 advanced v0.2 figure 3-29 ram write, output retained (wmode = 0) t cyc t ckh t ckl a 0 a 1 a 2 di 0 di 1 t as t ah t bks t ens t enh t ds t dh clk blk_b wen_b add di d n do t bkh d 2
proasic3 flash family fpgas advanced v0.2 3-53 figure 3-30 ram write, output as write data (wmode = 1) t cyc t ckh t ckl a 0 a 1 a 2 di 0 di 1 t as t ah t bks t ens t ds t dh clk blk_b wen_b add di t bkh do (flow-through) di 1 d n di 0 do (pipelined) di 0 di 1 d n di 2
proasic3 flash family fpgas 3-54 advanced v0.2 figure 3-31 one port write/other port read same figure 3-32 ram reset a 0 a 2 a 3 a 0 a 1 a 4 clk1 add1 clk2 add2 di1 d 0 d 2 d 3 d 0 d 1 d 0 do2 (flow-through) do2 (pipelined) t ckq2 t ckq1 t wro t as t ah t ds t dh t as t ah d n d n clk reset_b do d n t cyc t ckh t ckl t rstbq d m
proasic3 flash family fpgas advanced v0.2 3-55 timing characteristics table 3-68 ram4k9 commercial-case conditions: t j = 70c, worst case v cc = 1.425 v parameter description ?2 ?1 std. ?f units t as address setup time 0.30 0.34 0.40 0.48 ns t ah address hold time 0.00 0.00 0.00 0.00 ns t ens ren_b,wen_b setup time 0.20 0.22 0.26 0.32 ns t enh ren_b, wen_b hold time 0.03 0.03 0.04 0.05 ns t bks blk_b setup time 0.00 0.00 0.00 0.00 ns t bkh blk_b hold time 0.06 0.07 0.08 0.10 ns t ds input data (di) setup time 0.24 0.27 0.32 0.38 ns t dh input data (di) hold time 0.00 0.00 0.00 0.00 ns t ckq1 clock high to new data valid on do (output retained, wmode = 0) 1.73 1.97 2.32 2.79 ns clock high to new data valid on do (flow-through, wmode =1) 2.28 2.60 3.05 3.67 ns t ckq2 clock high to new data valid on do (pipelined) 0.85 0.97 1.14 1.37 ns t rstbq reset_b low to data out low on do (flow through) 0.98 1.12 1.31 1.57 ns reset_b low to data out low on do (pipelined) 0.98 1.12 1.31 1.57 ns t remrstb reset_b removal 0.00 0.00 0.00 0.00 ns t recrstb reset_b recovery 0.10 0.10 0.10 0.10 ns t mpwrstb reset_b minimum pulse width 0.22 0.25 0.29 0.35 ns t cyc clock cycle time 2.10 2.38 2.80 3.36 ns note: for specific junction temperature and voltage-supply levels, refer to table 3-6 on page 3-4 for derating values. table 3-69 ram512x18 commercial-case conditions: t j = 70c, worst case v cc = 1.425 v parameter description ?2 ?1 std. ?f units t as address setup time 0.30 0.34 0.40 0.48 ns t ah address hold time 0.00 0.00 0.00 0.00 ns t ens ren_b,wen_b setup ti me 0.14 0.16 0.19 0.23 ns t enh reb_b, wen_b hold time 0.02 0.03 0.03 0.04 ns t ds input data (di) setup time 0.22 0.25 0.30 0.36 ns td h input data (di) hold time 0.00 0.00 0.00 0.00 ns t ckq1 clock high to new data valid on do (output retained, wmode =0) 2.08 2.37 2.79 3.35 ns t ckq2 clock high to new data valid on do (pipelined) 0.85 0.97 1.14 1.37 ns t rstbq reset_b low to data out low on do (flow through) 0.98 1.12 1.31 1.57 ns reset_b low to data out low on do (pipelined) 0.98 1.12 1.31 1.57 ns t remrstb reset_b removal 0.00 0.00 0.00 0.00 ns t recrstb reset_b recovery 0.10 0.10 0.10 0.10 ns t mpwrstb reset_b minimum pulse width 0.22 0.25 0.29 0.35 ns t cyc clock cycle time 2.10 2.38 2.80 3.36 ns note: for specific junction temperature and voltage-supply levels, refer to table 3-6 on page 3-4 for derating values.
proasic3 flash family fpgas 3-56 advanced v0.2 fifo figure 3-33 fifo model fifo4k18 rw2 rd17 rw1 rd16 rw0 ww2 ww1 ww0 rd0 estop fstop full afull empty afval11 aempty afval10 afval0 aeval11 aeval10 aeval0 ren rblk rclk wen wblk wclk rpipe wd17 wd16 wd0 reset
proasic3 flash family fpgas advanced v0.2 3-57 timing waveforms figure 3-34 fifo reset figure 3-35 fifo reset, empty flag , and almost-empty flag match (a 0 ) t mpwrstb t rstfg t rstck t rstaf rclk/ wclk reset_b ef aef wa/ra (address counter) t rstfg t rstaf ff aff rclk no match no match dist = aef_th match (empty) t ckaf t rckef ef aef t cyc wa/ra (address counter)
proasic3 flash family fpgas 3-58 advanced v0.2 figure 3-36 fifo full and afull flag figure 3-37 empty flag and aempty flag deassertion figure 3-38 full and alfull deassertion no match no match dist = aff_th match (full) t ckaf t wckff t cyc wclk ff aff wa/ra (address counter) wclk wa/ra (address counter) match (empty) no match no match no match dist = aef_th + 1 no match rclk ef 1st rising edge after 1st write 2nd rising edge after 1st write t rckef t ckaf aef rclk wa/ra (address counter) match (full) no match no match no match dist = aff_th - 1 no match wclk ff 1st rising edge after 1st read 1st rising edge after 2nd read t wckf t ckaf aff
proasic3 flash family fpgas advanced v0.2 3-59 timing characteristics embedded from characteristics table 3-70 fifo commercial-case conditions: t j = 70c, v cc = 1.425 v parameter description ?2 ?1 std. ?f units t ens ren_b,wen_b setup time 0.14 0.16 0.19 0.23 ns t enh ren_b, wen_b hold time 0.06 0.07 0.08 0.10 ns t bks blk_b setup time 0.25 0.29 0.34 0.40 ns t bkh blk_b hold time 0.00 0.00 0.00 0.00 ns t ds input data (di) setup time 0.22 0.25 0.30 0.36 ns t dh input data (di) hold time 0.00 0.00 0.00 0.00 ns t ckq1 clock high to new data valid on do (flow-through) 2.28 2.60 3.05 3.67 ns t ckq2 clock high to new data valid on do (pipelined) 0.85 0.97 1.14 1.37 ns t rckef rclk high to empty flag valid 1.69 1.92 2.26 2.71 ns t wckff wclk high to full flag valid 1.61 1.83 2.15 2.58 ns t ckaf clock high to almost empty/full flag valid 3.62 4.12 4.85 5.82 ns t rstfg reset_b low to empty/full fl ag valid 1.71 1.94 2.28 2.74 ns t rstaf reset_b low to almost-empty/fu ll flag valid 3.58 4.08 4.80 5.77 ns t rstbq reset_b low to data out low on do (flow through) 0.98 1.12 1.31 1.57 ns reset_b low to data out low on do (pipelined) 0.98 1.12 1.31 1.57 ns t remrstb reset_b removal 0.00 0.00 0.00 0.00 ns t recrstb reset_b recovery 0.10 0.10 0.10 0.10 ns t mpwrstb reset_b minimum pulse width 0.21 0.24 0.29 0.34 ns t cyc clock cycle time 2.06 2.33 2.75 3.29 ns note: for specific junction temperature and voltage-supply levels, refer to table 3-6 on page 3-4 for derating values. figure 3-39 timing diagram addr do a 0 d 0 d 1 a 1 t a t a
proasic3 flash family fpgas 3-60 advanced v0.2 timing characteristics jtag 1532 characteristics jtag timing delays do not include jtag i/os. to obtain complete jtag timing, add i/ o buffer delays to the corresponding standard selected , refer to the i/o timing char acteristics for more details. timing characteristics table 3-71 embedded from access time parameter description ?2 ?1 std. units t a data access time 10 10 10 ns table 3-72 jtag 1532 commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v parameter description ?2 ?1 std. units t disu test data input setup time ns t dihd test data input hold time ns t tmssu test mode select setup time ns t tmdhd test mode select hold time ns t tck2q clock to q (data out) ns t rstb2q reset to q (data out) ns f tckmax tck maximum frequency 20/40 20/40 20/40 mhz t trstrem resetb removal time ns t trstrec resetb recovery time ns t trstmpw resetb minimum pulse ns note: for specific junction temperature and voltage-supply levels, refer to table 3-6 on page 3-4 for derating values.
proasic3 flash family fpgas advanced v0.2 4 -1 package pin assignments 132-pin qfn note for package manufacturing and environmental information, visit resource center at http://www.actel.com/products/ rescenter/package/index.html . a48 a36 a25 a1 a12 a37 a13 a24 b44 b33 b23 b34 b12 b22 c40 c30 c21 b1 b11 c1 c10 c31 c11 c20 optional corner pad (4x) pin a1 mark
proasic3 flash family fpgas 4-2 advanced v0.2 100-pin vqfp note for package manufacturing and environmental information, visit resource center at http://www.actel.com/products/ rescenter/package/index.html . 1 100-pin vqfp 100
proasic3 flash family fpgas advanced v0.2 4-3 100-pin vqfp* pin number A3P060 function 1gnd 2 gaa2/io51rsb1 3 io52rsb1 4 gab2/io53rsb1 5 io95rsb1 6 gac2/io94rsb1 7 io93rsb1 8 io92rsb1 9gnd 10 gfb1/io87rsb1 11 gfb0/io86rsb1 12 v complf 13 gfa0/io85rsb1 14 v ccplf 15 gfa1/io84rsb1 16 gfa2/io83rsb1 17 v cc 18 v cci b1 19 gec1/io77rsb1 20 geb1/io75rsb1 21 geb0/io74rsb1 22 gea1/io73rsb1 23 gea0/io72rsb1 24 vmv1 25 gndq 26 gea2/io71rsb1 27 geb2/io70rsb1 28 gec2/io69rsb1 29 io68rsb1 30 io67rsb1 31 io66rsb1 32 io65rsb1 33 io64rsb1 34 io63rsb1 35 io62rsb1 36 io61rsb1 37 v cc 38 gnd 39 v cci b1 40 io60rsb1 41 io59rsb1 42 io58rsb1 43 gdc2/io57rsb1 44 gdb2/io56rsb1 45 gda2/io55rsb1 46 io54rsb1 47 tck 48 tdi 49 tms 50 nc 51 gnd 52 v pump 53 nc 54 tdo 55 trst 56 v jtag 57 gda1/io49rsb0 58 gdc0/io46rsb0 59 gdc1/io45rsb0 60 io44rsb0 61 gcb2/io42rsb0 62 gca0/io40rsb0 63 gca1/io39rsb0 64 gcc0/io36rsb0 65 gcc1/io35rsb0 66 v cci b0 67 gnd 68 v cc 69 io31rsb0 70 gbc2/io29rsb0 71 gbb2/io27rsb0 72 io26rsb0 100-pin vqfp* pin number A3P060 function 73 gba2/io25rsb0 74 vmv0 75 gndq 76 gba1/io24rsb0 77 gba0/io23rsb0 78 gbb1/io22rsb0 79 gbb0/io21rsb0 80 gbc1/io20rsb0 81 gbc0/io19rsb0 82 io18rsb0 83 io17rsb0 84 io15rsb0 85 io13rsb0 86 io11rsb0 87 v cci b0 88 gnd 89 v cc 90 io10rsb0 91 io09rsb0 92 io08rsb0 93 gac1/io07rsb0 94 gac0/io06rsb0 95 gab1/io05rsb0 96 gab0/io04rsb0 97 gaa1/io03rsb0 98 gaa0/io02rsb0 99 io01rsb0 100 io00rsb0 100-pin vqfp* pin number A3P060 function note: *refer to the "user i/o naming convention" section on page 2-44 .
proasic3 flash family fpgas 4-4 advanced v0.2 100-pin vqfp* pin number a3p125 function 1gnd 2 gaa2/io67rsb1 3 io68rsb1 4 gab2/io69rsb1 5 io132rsb1 6 gac2/io131rsb1 7 io130rsb1 8 io129rsb1 9gnd 10 gfb1/io124rsb1 11 gfb0/io123rsb1 12 v complf 13 gfa0/io122rsb1 14 v ccplf 15 gfa1/io121rsb1 16 gfa2/io120rsb1 17 v cc 18 v cci b1 19 gec0/io111rsb1 20 geb1/io110rsb1 21 geb0/io109rsb1 22 gea1/io108rsb1 23 gea0/io107rsb1 24 vmv1 25 gndq 26 gea2/io106rsb1 27 geb2/io105rsb1 28 gec2/io104rsb1 29 io102rsb1 30 io100rsb1 31 io99rsb1 32 io97rsb1 33 io96rsb1 34 io95rsb1 35 io94rsb1 36 io93rsb1 37 v cc 38 gnd 39 v cci b1 40 io87rsb1 41 io84rsb1 42 io81rsb1 43 io75rsb1 44 gdc2/io72rsb1 45 gdb2/io71rsb1 46 gda2/io70rsb1 47 tck 48 tdi 49 tms 50 vmv1 51 gnd 52 v pump 53 nc 54 tdo 55 trst 56 v jtag 57 gda1/io65rsb0 58 gdc0/io62rsb0 59 gdc1/io61rsb0 60 gcc2/io59rsb0 61 gcb2/io58rsb0 62 gca0/io56rsb0 63 gca1/io55rsb0 64 gcc0/io52rsb0 65 gcc1/io51rsb0 66 v cci b0 67 gnd 68 v cc 69 io47rsb0 70 gbc2/io45rsb0 71 gbb2/io43rsb0 72 io42rsb0 73 gba2/io41rsb0 74 vmv0 75 gndq 76 gba1/io40rsb0 100-pin vqfp* pin number a3p125 function 77 gba0/io39rsb0 78 gbb1/io38rsb0 79 gbb0/io37rsb0 80 gbc1/io36rsb0 81 gbc0/io35rsb0 82 io32rsb0 83 io28rsb0 84 io25rsb0 85 io22rsb0 86 io19rsb0 87 v cci b0 88 gnd 89 v cc 90 io15rsb0 91 io13rsb0 92 io11rsb0 93 io09rsb0 94 io07rsb0 95 gac1/io05rsb0 96 gac0/io04rsb0 97 gab1/io03rsb0 98 gab0/io02rsb0 99 gaa1/io01rsb0 100 gaa0/io00rsb0 100-pin vqfp* pin number a3p125 function note: *refer to the "user i/o naming convention" section on page 2-44 .
proasic3 flash family fpgas advanced v0.2 4-5 100-pin vqfp* pin number a3p250 function 1gnd 2 gaa2/io118pdb3 3 io118ndb3 4 gab2/io117pdb3 5 io117ndb3 6 gac2/io116pdb3 7 io116ndb3 8 io112psb3 9gnd 10 gfb1/io109pdb3 11 gfb0/io109ndb3 12 v complf 13 gfa0/io108npb3 14 v ccplf 15 gfa1/io108ppb3 16 gfa2/io107psb3 17 v cc 18 v cci b3 19 gfc2/io105psb3 20 gec1/io100pdb3 21 gec0/io100ndb3 22 gea1/io98pdb3 23 gea0/io98ndb3 24 vmv3 25 gndq 26 gea2/io97rsb2 27 geb2/io96rsb2 28 gec2/io95rsb2 29 io93rsb2 30 io92rsb2 31 io91rsb2 32 io90rsb2 33 io88rsb2 34 io86rsb2 35 io85rsb2 36 io84rsb2 37 v cc 38 gnd 39 v cci b2 40 io77rsb2 41 io74rsb2 42 io71rsb2 43 gdc2/io63rsb2 44 gdb2/io62rsb2 45 gda2/io61rsb2 46 gndq 47 tck 48 tdi 49 tms 50 vmv2 51 gnd 52 v pump 53 nc 54 tdo 55 trst 56 v jtag 57 gda1/io60psb1 58 gdc0/io58ndb1 59 gdc1/io58pdb1 60 io52ndb1 61 gcb2/io52pdb1 62 gca1/io50pdb1 63 gca0/io50ndb1 64 gcc0/io48ndb1 65 gcc1/io48pdb1 66 v cci b1 67 gnd 68 v cc 69 io43ndb1 70 gbc2/io43pdb1 71 gbb2/io42psb1 72 io41ndb1 100-pin vqfp* pin number a3p250 function 73 gba2/io41pdb1 74 vmv1 75 gndq 76 gba1/io40rsb0 77 gba0/io39rsb0 78 gbb1/io38rsb0 79 gbb0/io37rsb0 80 gbc1/io36rsb0 81 gbc0/io35rsb0 82 io29rsb0 83 io27rsb0 84 io25rsb0 85 io23rsb0 86 io21rsb0 87 v cci b0 88 gnd 89 v cc 90 io15rsb0 91 io13rsb0 92 io11rsb0 93 gac1/io05rsb0 94 gac0/io04rsb0 95 gab1/io03rsb0 96 gab0/io02rsb0 97 gaa1/io01rsb0 98 gaa0/io00rsb0 99 gndq 100 vmv0 100-pin vqfp* pin number a3p250 function note: *refer to the "user i/o naming convention" section on page 2-44 .
proasic3 flash family fpgas 4-6 advanced v0.2 144-pin tqfp note for package manufacturing and environmental information, visit resource center at http://www.actel.com/products/ rescenter/package/index.html . 1 144 144-pin tqfp
proasic3 flash family fpgas advanced v0.2 4-7 144-pin tqfp* pin number A3P060 function 1 gaa2/io51rsb1 2 io52rsb1 3 gab2/io53rsb1 4 io95rsb1 5 gac2/io94rsb1 6 io93rsb1 7 io92rsb1 8 io91rsb1 9v cc 10 gnd 11 v cci b1 12 io90rsb1 13 gfc1/io89rsb1 14 gfc0/io88rsb1 15 gfb1/io87rsb1 16 gfb0/io86rsb1 17 v complf 18 gfa0/io85rsb1 19 v ccplf 20 gfa1/io84rsb1 21 gfa2/io83rsb1 22 gfb2/io82rsb1 23 gfc2/io81rsb1 24 io80rsb1 25 io79rsb1 26 io78rsb1 27 gnd 28 v cci b1 29 gec1/io77rsb1 30 gec0/io76rsb1 31 geb1/io75rsb1 32 geb0/io74rsb1 33 gea1/io73rsb1 34 gea0/io72rsb1 35 vmv1 36 gndq 37 nc 38 gea2/io71rsb1 39 geb2/io70rsb1 40 gec2/io69rsb1 41 io68rsb1 42 io67rsb1 43 io66rsb1 44 io65rsb1 45 v cc 46 gnd 47 v cci b1 48 nc 49 io64rsb1 50 nc 51 io63rsb1 52 nc 53 io62rsb1 54 nc 55 io61rsb1 56 nc 57 nc 58 io60rsb1 59 io59rsb1 60 io58rsb1 61 gdc2/io57rsb1 62 nc 63 gnd 64 nc 65 gdb2/io56rsb1 66 gda2/io55rsb1 67 io54rsb1 68 gndq 69 tck 70 tdi 71 tms 72 vmv1 144-pin tqfp* pin number A3P060 function 73 v pump 74 nc 75 tdo 76 trst 77 v jtag 78 gda0/io50rsb0 79 gdb0/io48rsb0 80 gdb1/io47rsb0 81 v cci b0 82 gnd 83 io44rsb0 84 gcc2/io43rsb0 85 gcb2/io42rsb0 86 gca2/io41rsb0 87 gca0/io40rsb0 88 gca1/io39rsb0 89 gcb0/io38rsb0 90 gcb1/io37rsb0 91 gcc0/io36rsb0 92 gcc1/io35rsb0 93 io34rsb0 94 io33rsb0 95 nc 96 nc 97 nc 98 v cci b0 99 gnd 100 v cc 101 io30rsb0 102 gbc2/io29rsb0 103 io28rsb0 104 gbb2/io27rsb0 105 io26rsb0 106 gba2/io25rsb0 107 vmv0 108 gndq 144-pin tqfp* pin number A3P060 function note: *refer to the "user i/o naming convention" section on page 2-44 .
proasic3 flash family fpgas 4-8 advanced v0.2 109 nc 110 nc 111 gba1/io24rsb0 112 gba0/io23rsb0 113 gbb1/io22rsb0 114 gbb0/io21rsb0 115 gbc1/io20rsb0 116 gbc0/io19rsb0 117 v cci b0 118 gnd 119 v cc 120 io18rsb0 121 io17rsb0 122 io16rsb0 123 io15rsb0 124 io14rsb0 125 io13rsb0 126 io12rsb0 127 io11rsb0 128 nc 129 io10rsb0 130 io09rsb0 131 io08rsb0 132 gac1/io07rsb0 133 gac0/io06rsb0 134 nc 135 gnd 136 nc 137 gab1/io05rsb0 138 gab0/io04rsb0 139 gaa1/io03rsb0 140 gaa0/io02rsb0 141 io01rsb0 142 io00rsb0 143 gndq 144 vmv0 144-pin tqfp* pin number A3P060 function note: *refer to the "user i/o naming convention" section on page 2-44 .
proasic3 flash family fpgas advanced v0.2 4-9 144_pin tqfp* pin number a3p125 function 1 gaa2/io67rsb1 2 io68rsb1 3 gab2/io69rsb1 4 io132rsb1 5 gac2/io131rsb1 6 io130rsb1 7 io129rsb1 8 io128rsb1 9v cc 10 gnd 11 v cci b1 12 io127rsb1 13 gfc1/io126rsb1 14 gfc0/io125rsb1 15 gfb1/io124rsb1 16 gfb0/io123rsb1 17 v complf 18 gfa0/io122rsb1 19 v ccplf 20 gfa1/io121rsb1 21 gfa2/io120rsb1 22 gfb2/io119rsb1 23 gfc2/io118rsb1 24 io117rsb1 25 io116rsb1 26 io115rsb1 27 gnd 28 v cci b1 29 gec1/io112rsb1 30 gec0/io111rsb1 31 geb1/io110rsb1 32 geb0/io109rsb1 33 gea1/io108rsb1 34 gea0/io107rsb1 35 vmv1 36 gndq 37 nc 38 gea2/io106rsb1 39 geb2/io105rsb1 40 gec2/io104rsb1 41 io103rsb1 42 io102rsb1 43 io101rsb1 44 io100rsb1 45 v cc 46 gnd 47 v cci b1 48 io99rsb1 49 io97rsb1 50 io95rsb1 51 io93rsb1 52 io92rsb1 53 io90rsb1 54 io88rsb1 55 io86rsb1 56 io84rsb1 57 io83rsb1 58 io82rsb1 59 io81rsb1 60 io80rsb1 61 io79rsb1 62 v cc 63 gnd 64 v cci b1 65 gdc2/io72rsb1 66 gdb2/io71rsb1 67 gda2/io70rsb1 68 gndq 69 tck 70 tdi 71 tms 72 vmv1 144_pin tqfp* pin number a3p125 function 73 v pump 74 nc 75 tdo 76 trst 77 v jtag 78 gda0/io66rsb0 79 gdb0/io64rsb0 80 gdb1/io63rsb0 81 v cci b0 82 gnd 83 io60rsb0 84 gcc2/io59rsb0 85 gcb2/io58rsb0 86 gca2/io57rsb0 87 gca0/io56rsb0 88 gca1/io55rsb0 89 gcb0/io54rsb0 90 gcb1/io53rsb0 91 gcc0/io52rsb0 92 gcc1/io51rsb0 93 io50rsb0 94 io49rsb0 95 nc 96 nc 97 nc 98 v cci b0 99 gnd 100 v cc 101 io47rsb0 102 gbc2/io45rsb0 103 io44rsb0 104 gbb2/io43rsb0 105 io42rsb0 106 gba2/io41rsb0 107 vmv0 108 gndq 144_pin tqfp* pin number a3p125 function note: *refer to the "user i/o naming convention" section on page 2-44 .
proasic3 flash family fpgas 4-10 advanced v0.2 109 gba1/io40rsb0 110 gba0/io39rsb0 111 gbb1/io38rsb0 112 gbb0/io37rsb0 113 gbc1/io36rsb0 114 gbc0/io35rsb0 115 io34rsb0 116 io33rsb0 117 v cci b0 118 gnd 119 v cc 120 io29rsb0 121 io28rsb0 122 io27rsb0 123 io25rsb0 124 io23rsb0 125 io21rsb0 126 io19rsb0 127 io17rsb0 128 io16rsb0 129 io14rsb0 130 io12rsb0 131 io10rsb0 132 io08rsb0 133 io06rsb0 134 v cci b0 135 gnd 136 v cc 137 gac1/io05rsb0 138 gac0/io04rsb0 139 gab1/io03rsb0 140 gab0/io02rsb0 141 gaa1/io01rsb0 142 gaa0/io00rsb0 143 gndq 144 vmv0 144_pin tqfp* pin number a3p125 function note: *refer to the "user i/o naming convention" section on page 2-44 .
proasic3 flash family fpgas advanced v0.2 4-11 208-pin pqfp note for package manufacturing and environmental information, visit resource center at http://www.actel.com/products/ rescenter/package/index.html . 208-pin pqfp 1 208
proasic3 flash family fpgas 4-12 advanced v0.2 208-pin pqfp* pin number a3p125 function 1gnd 2 gaa2/io67rsb1 3 io68rsb1 4 gab2/io69rsb1 5 io132rsb1 6 gac2/io131rsb1 7nc 8nc 9 io130rsb1 10 io129rsb1 11 nc 12 io128rsb1 13 nc 14 nc 15 nc 16 v cc 17 gnd 18 v cci b1 19 io127rsb1 20 nc 21 gfc1/io126rsb1 22 gfc0/io125rsb1 23 gfb1/io124rsb1 24 gfb0/io123rsb1 25 v complf 26 gfa0/io122rsb1 27 v ccplf 28 gfa1/io121rsb1 29 gnd 30 gfa2/io120rsb1 31 nc 32 gfb2/io119rsb1 33 nc 34 gfc2/io118rsb1 35 io117rsb1 36 nc 37 io116rsb1 38 io115rsb1 39 nc 40 v cci b1 41 gnd 42 io114rsb1 43 io113rsb1 44 gec1/io112rsb1 45 gec0/io111rsb1 46 geb1/io110rsb1 47 geb0/io109rsb1 48 gea1/io108rsb1 49 gea0/io107rsb1 50 vmv1 51 gndq 52 gnd 53 nc 54 nc 55 gea2/io106rsb1 56 geb2/io105rsb1 57 gec2/io104rsb1 58 io103rsb1 59 io102rsb1 60 io101rsb1 61 io100rsb1 62 v cci b1 63 io99rsb1 64 io98rsb1 65 gnd 66 io97rsb1 67 io96rsb1 68 io95rsb1 69 io94rsb1 70 io93rsb1 71 v cc 72 v cci b1 73 io92rsb1 74 io91rsb1 75 io90rsb1 76 io89rsb1 208-pin pqfp* pin number a3p125 function 77 io88rsb1 78 io87rsb1 79 io86rsb1 80 io85rsb1 81 gnd 82 io84rsb1 83 io83rsb1 84 io82rsb1 85 io81rsb1 86 io80rsb1 87 io79rsb1 88 v cc 89 v cci b1 90 io78rsb1 91 io77rsb1 92 io76rsb1 93 io75rsb1 94 io74rsb1 95 io73rsb1 96 gdc2/io72rsb1 97 gnd 98 gdb2/io71rsb1 99 gda2/io70rsb1 100 gndq 101 tck 102 tdi 103 tms 104 vmv1 105 gnd 106 v pump 107 nc 108 tdo 109 trst 110 v jtag 111 gda0/io66rsb0 112 gda1/io65rsb0 113 gdb0/io64rsb0 114 gdb1/io63rsb0 208-pin pqfp* pin number a3p125 function note: *refer to the "user i/o naming convention" section on page 2-44 .
proasic3 flash family fpgas advanced v0.2 4-13 115 gdc0/io62rsb0 116 gdc1/io61rsb0 117 nc 118 nc 119 nc 120 nc 121 nc 122 gnd 123 v cci b0 124 nc 125 nc 126 v cc 127 io60rsb0 128 gcc2/io59rsb0 129 gcb2/io58rsb0 130 gnd 131 gca2/io57rsb0 132 gca0/io56rsb0 133 gca1/io55rsb0 134 gcb0/io54rsb0 135 gcb1/io53rsb0 136 gcc0/io52rsb0 137 gcc1/io51rsb0 138 io50rsb0 139 io49rsb0 140 v cci b0 141 gnd 142 v cc 143 io48rsb0 144 io47rsb0 145 io46rsb0 146 nc 147 nc 148 nc 149 gbc2/io45rsb0 150 io44rsb0 151 gbb2/io43rsb0 152 io42rsb0 208-pin pqfp* pin number a3p125 function 153 gba2/io41rsb0 154 vmv0 155 gndq 156 gnd 157 nc 158 gba1/io40rsb0 159 gba0/io39rsb0 160 gbb1/io38rsb0 161 gbb0/io37rsb0 162 gnd 163 gbc1/io36rsb0 164 gbc0/io35rsb0 165 io34rsb0 166 io33rsb0 167 io32rsb0 168 io31rsb0 169 io30rsb0 170 v cci b0 171 v cc 172 io29rsb0 173 io28rsb0 174 io27rsb0 175 io26rsb0 176 io25rsb0 177 io24rsb0 178 gnd 179 io23rsb0 180 io22rsb0 181 io21rsb0 182 io20rsb0 183 io19rsb0 184 io18rsb0 185 io17rsb0 186 v cci b0 187 v cc 188 io16rsb0 189 io15rsb0 190 io14rsb0 208-pin pqfp* pin number a3p125 function 191 io13rsb0 192 io12rsb0 193 io11rsb0 194 io10rsb0 195 gnd 196 io09rsb0 197 io08rsb0 198 io07rsb0 199 io06rsb0 200 v cci b0 201 gac1/io05rsb0 202 gac0/io04rsb0 203 gab1/io03rsb0 204 gab0/io02rsb0 205 gaa1/io01rsb0 206 gaa0/io00rsb0 207 gndq 208 vmv0 208-pin pqfp* pin number a3p125 function note: *refer to the "user i/o naming convention" section on page 2-44 .
proasic3 flash family fpgas 4-14 advanced v0.2 208-pin pqfp* pin number a3p250 function 1gnd 2 gaa2/io118pdb3 3 io118ndb3 4 gab2/io117pdb3 5 io117ndb3 6 gac2/io116pdb3 7 io116ndb3 8 io115pdb3 9 io115ndb3 10 io114pdb3 11 io114ndb3 12 io113pdb3 13 io113ndb3 14 io112pdb3 15 io112ndb3 16 v cc 17 gnd 18 v cci b3 19 io111pdb3 20 io111ndb3 21 gfc1/io110pdb3 22 gfc0/io110ndb3 23 gfb1/io109pdb3 24 gfb0/io109ndb3 25 v complf 26 gfa0/io108npb3 27 v ccplf 28 gfa1/io108ppb3 29 gnd 30 gfa2/io107pdb3 31 io107ndb3 32 gfb2/io106pdb3 33 io106ndb3 34 gfc2/io105pdb3 35 io105ndb3 36 nc 37 io104pdb3 38 io104ndb3 39 io103psb3 40 v cci b3 41 gnd 42 io101pdb3 43 io101ndb3 44 gec1/io100pdb3 45 gec0/io100ndb3 46 geb1/io99pdb3 47 geb0/io99ndb3 48 gea1/io98pdb3 49 gea0/io98ndb3 50 vmv3 51 gndq 52 gnd 53 nc 54 nc 55 gea2/io97rsb2 56 geb2/io96rsb2 57 gec2/io95rsb2 58 io94rsb2 59 io93rsb2 60 io92rsb2 61 io91rsb2 62 v cci b2 63 io90rsb2 64 io89rsb2 65 gnd 66 io88rsb2 67 io87rsb2 68 io86rsb2 69 io85rsb2 70 io84rsb2 71 v cc 72 v cci b2 73 io83rsb2 74 io82rsb2 75 io81rsb2 76 io80rsb2 208-pin pqfp* pin number a3p250 function 77 io79rsb2 78 io78rsb2 79 io77rsb2 80 io76rsb2 81 gnd 82 io75rsb2 83 io74rsb2 84 io73rsb2 85 io72rsb2 86 io71rsb2 87 io70rsb2 88 v cc 89 v cci b2 90 io69rsb2 91 io68rsb2 92 io67rsb2 93 io66rsb2 94 io65rsb2 95 io64rsb2 96 gdc2/io63rsb2 97 gnd 98 gdb2/io62rsb2 99 gda2/io61rsb2 100 gndq 101 tck 102 tdi 103 tms 104 vmv2 105 gnd 106 v pump 107 nc 108 tdo 109 trst 110 v jtag 111 gda0/io60ndb1 112 gda1/io60pdb1 113 gdb0/io59ndb1 114 gdb1/io59pdb1 208-pin pqfp* pin number a3p250 function note: *refer to the "user i/o naming convention" section on page 2-44 .
proasic3 flash family fpgas advanced v0.2 4-15 115 gdc0/io58ndb1 116 gdc1/io58pdb1 117 io57ndb1 118 io57pdb1 119 io56ndb1 120 io56pdb1 121 io55rsb1 122 gnd 123 v cci b1 124 nc 125 nc 126 v cc 127 io53ndb1 128 gcc2/io53pdb1 129 gcb2/io52psb1 130 gnd 131 gca2/io51psb1 132 gca1/io50pdb1 133 gca0/io50ndb1 134 gcb0/io49ndb1 135 gcb1/io49pdb1 136 gcc0/io48ndb1 137 gcc1/io48pdb1 138 io47ndb1 139 io47pdb1 140 v cci b1 141 gnd 142 v cc 143 io46rsb1 144 io45ndb1 145 io45pdb1 146 io44ndb1 147 io44pdb1 148 io43ndb1 149 gbc2/io43pdb1 150 io42ndb1 151 gbb2/io42pdb1 152 io41ndb1 208-pin pqfp* pin number a3p250 function 153 gba2/io41pdb1 154 vmv1 155 gndq 156 gnd 157 nc 158 gba1/io40rsb0 159 gba0/io39rsb0 160 gbb1/io38rsb0 161 gbb0/io37rsb0 162 gnd 163 gbc1/io36rsb0 164 gbc0/io35rsb0 165 io34rsb0 166 io33rsb0 167 io32rsb0 168 io31rsb0 169 io30rsb0 170 v cci b0 171 v cc 172 io29rsb0 173 io28rsb0 174 io27rsb0 175 io26rsb0 176 io25rsb0 177 io24rsb0 178 gnd 179 io23rsb0 180 io22rsb0 181 io21rsb0 182 io20rsb0 183 io19rsb0 184 io18rsb0 185 io17rsb0 186 v cci b0 187 v cc 188 io16rsb0 189 io15rsb0 190 io14rsb0 208-pin pqfp* pin number a3p250 function 191 io13rsb0 192 io12rsb0 193 io11rsb0 194 io10rsb0 195 gnd 196 io09rsb0 197 io08rsb0 198 io07rsb0 199 io06rsb0 200 v cci b0 201 gac1/io05rsb0 202 gac0/io04rsb0 203 gab1/io03rsb0 204 gab0/io02rsb0 205 gaa1/io01rsb0 206 gaa0/io00rsb0 207 gndq 208 vmv0 208-pin pqfp* pin number a3p250 function note: *refer to the "user i/o naming convention" section on page 2-44 .
proasic3 flash family fpgas 4-16 advanced v0.2 208-pin pqfp* pin number a3p400 function 1gnd 2 gaa2/io155pdb3 3 io155ndb3 4 gab2/io154pdb3 5 io154ndb3 6 gac2/io153pdb3 7 io153ndb3 8 io152pdb3 9 io152ndb3 10 io151pdb3 11 io151ndb3 12 io150pdb3 13 io150ndb3 14 io149pdb3 15 io149ndb3 16 v cc 17 gnd 18 v cci b3 19 io148pdb3 20 io148ndb3 21 gfc1/io147pdb3 22 gfc0/io147ndb3 23 gfb1/io146pdb3 24 gfb0/io146ndb3 25 v complf 26 gfa0/io145npb3 27 v ccplf 28 gfa1/io145ppb3 29 gnd 30 gfa2/io144pdb3 31 io144ndb3 32 gfb2/io143pdb3 33 io143ndb3 34 gfc2/io142pdb3 35 io142ndb3 36 nc 37 io141pdb3 38 io141ndb3 39 io140psb3 40 v cci b3 41 gnd 42 io138pdb3 43 io138ndb3 44 gec1/io137pdb3 45 gec0/io137ndb3 46 geb1/io136pdb3 47 geb0/io136ndb3 48 gea1/io135pdb3 49 gea0/io135ndb3 50 vmv3 51 gndq 52 gnd 53 nc 54 nc 55 gea2/io134rsb2 56 geb2/io133rsb2 57 gec2/io132rsb2 58 io131rsb2 59 io130rsb2 60 io129rsb2 61 io128rsb2 62 v cci b2 63 io126rsb2 64 io124rsb2 65 gnd 66 io122rsb2 67 io120rsb2 68 io118rsb2 69 io116rsb2 70 io114rsb2 71 v cc 72 v cci b2 73 io112rsb2 74 io111rsb2 75 io110rsb2 76 io109rsb2 208-pin pqfp* pin number a3p400 function 77 io108rsb2 78 io107rsb2 79 io106rsb2 80 io103rsb2 81 gnd 82 io102rsb2 83 io101rsb2 84 io100rsb2 85 io99rsb2 86 io98rsb2 87 io97rsb2 88 v cc 89 v cci b2 90 io94rsb2 91 io92rsb2 92 io90rsb2 93 io88rsb2 94 io86rsb2 95 io84rsb2 96 gdc2/io82rsb2 97 gnd 98 gdb2/io81rsb2 99 gda2/io80rsb2 100 gndq 101 tck 102 tdi 103 tms 104 vmv2 105 gnd 106 v pump 107 nc 108 tdo 109 trst 110 v jtag 111 gda0/io79ndb1 112 gda1/io79pdb1 113 gdb0/io78ndb1 114 gdb1/io78pdb1 208-pin pqfp* pin number a3p400 function note: *refer to the "user i/o naming convention" section on page 2-44 .
proasic3 flash family fpgas advanced v0.2 4-17 115 gdc0/io77ndb1 116 gdc1/io77pdb1 117 io76ndb1 118 io76pdb1 119 io75ndb1 120 io75pdb1 121 io74rsb1 122 gnd 123 v cci b1 124 nc 125 nc 126 v cc 127 io73psb1 128 gcc2/io72psb1 129 gcb2/io71psb1 130 gnd 131 gca2/io70psb1 132 gca1/io69pdb1 133 gca0/io69ndb1 134 gcb0/io68ndb1 135 gcb1/io68pdb1 136 gcc0/io67ndb1 137 gcc1/io67pdb1 138 io66ndb1 139 io66pdb1 140 v cci b1 141 gnd 142 v cc 143 io65rsb1 144 io64ndb1 145 io64pdb1 146 io63ndb1 147 io63pdb1 148 io62ndb1 149 gbc2/io62pdb1 150 io61ndb1 151 gbb2/io61pdb1 152 io60ndb1 208-pin pqfp* pin number a3p400 function 153 gba2/io60pdb1 154 vmv1 155 gndq 156 gnd 157 nc 158 gba1/io59rsb0 159 gba0/io58rsb0 160 gbb1/io57rsb0 161 gbb0/io56rsb0 162 gnd 163 gbc1/io55rsb0 164 gbc0/io54rsb0 165 io52rsb0 166 io50rsb0 167 io48rsb0 168 io46rsb0 169 io44rsb0 170 v cci b0 171 v cc 172 io37rsb0 173 io36rsb0 174 io35rsb0 175 io34rsb0 176 io33rsb0 177 io32rsb0 178 gnd 179 io31rsb0 180 io30rsb0 181 io29rsb0 182 io28rsb0 183 io27rsb0 184 io25rsb0 185 io23rsb0 186 v cci b0 187 v cc 188 io19rsb0 189 io17rsb0 190 io15rsb0 208-pin pqfp* pin number a3p400 function 191 io13rsb0 192 io12rsb0 193 io11rsb0 194 io10rsb0 195 gnd 196 io09rsb0 197 io08rsb0 198 io07rsb0 199 io06rsb0 200 v cci b0 201 gac1/io05rsb0 202 gac0/io04rsb0 203 gab1/io03rsb0 204 gab0/io02rsb0 205 gaa1/io01rsb0 206 gaa0/io00rsb0 207 gndq 208 vmv0 208-pin pqfp* pin number a3p400 function note: *refer to the "user i/o naming convention" section on page 2-44 .
proasic3 flash family fpgas 4-18 advanced v0.2 208-pin pqfp* pin number a3p600 function 1gnd 2 gaa2/io170pdb3 3 io170ndb3 4 gab2/io169pdb3 5 io169ndb3 6 gac2/io168pdb3 7 io168ndb3 8 io167pdb3 9 io167ndb3 10 io166pdb3 11 io166ndb3 12 io165pdb3 13 io165ndb3 14 io164pdb3 15 io164ndb3 16 v cc 17 gnd 18 v cci b3 19 io163pdb3 20 io163ndb3 21 gfc1/io161pdb3 22 gfc0/io161ndb3 23 gfb1/io160pdb3 24 gfb0/io160ndb3 25 v complf 26 gfa0/io159npb3 27 v ccplf 28 gfa1/io159ppb3 29 gnd 30 gfa2/io158pdb3 31 io158ndb3 32 gfb2/io157pdb3 33 io157ndb3 34 gfc2/io156pdb3 35 io156ndb3 36 v cc 37 io147pdb3 38 io147ndb3 39 io146psb3 40 v cci b3 41 gnd 42 io145pdb3 43 io145ndb3 44 gec1/io144pdb3 45 gec0/io144ndb3 46 geb1/io143pdb3 47 geb0/io143ndb3 48 gea1/io142pdb3 49 gea0/io142ndb3 50 vmv3 51 gndq 52 gnd 53 nc 54 gea2/io141rsb2 55 geb2/io140rsb2 56 gec2/io139rsb2 57 io138rsb2 58 io137rsb2 59 io136rsb2 60 io135rsb2 61 io134rsb2 62 v cci b2 63 io133rsb2 64 io131rsb2 65 gnd 66 io129rsb2 67 io127rsb2 68 io125rsb2 69 io123rsb2 70 io121rsb2 71 v cc 72 v cci b2 73 io118rsb2 74 io117rsb2 75 io116rsb2 76 io115rsb2 208-pin pqfp* pin number a3p600 function 77 io114rsb2 78 io113rsb2 79 io112rsb2 80 io110rsb2 81 gnd 82 io109rsb2 83 io108rsb2 84 io107rsb2 85 io106rsb2 86 io105rsb2 87 io104rsb2 88 v cc 89 v cci b2 90 io102rsb2 91 io100rsb2 92 io98rsb2 93 io96rsb2 94 io94rsb2 95 io90rsb2 96 gdc2/io89rsb2 97 gnd 98 gdb2/io88rsb2 99 gda2/io87rsb2 100 gndq 101 tck 102 tdi 103 tms 104 vmv2 105 gnd 106 v pump 107 gndq 108 tdo 109 trst 110 v jtag 111 gda0/io86ndb1 112 gda1/io86pdb1 113 gdb0/io85ndb1 114 gdb1/io85pdb1 208-pin pqfp* pin number a3p600 function note: *refer to the "user i/o naming convention" section on page 2-44 .
proasic3 flash family fpgas advanced v0.2 4-19 115 gdc0/io84ndb1 116 gdc1/io84pdb1 117 io82ndb1 118 io82pdb1 119 io80ndb1 120 io80pdb1 121 io79psb1 122 gnd 123 v cci b1 124 io75ndb1 125 io75pdb1 126 nc 127 io73ndb1 128 gcc2/io73pdb1 129 gcb2/io72psb1 130 gnd 131 gca2/io71psb1 132 gca1/io70pdb1 133 gca0/io70ndb1 134 gcb0/io69ndb1 135 gcb1/io69pdb1 136 gcc0/io68ndb1 137 gcc1/io68pdb1 138 io66ndb1 139 io66pdb1 140 v cci b1 141 gnd 142 v cc 143 io65psb1 144 io64ndb1 145 io64pdb1 146 io63ndb1 147 io63pdb1 148 io62ndb1 149 gbc2/io62pdb1 150 io61ndb1 151 gbb2/io61pdb1 152 io60ndb1 208-pin pqfp* pin number a3p600 function 153 gba2/io60pdb1 154 vmv1 155 gndq 156 gnd 157 nc 158 gba1/io59rsb0 159 gba0/io58rsb0 160 gbb1/io57rsb0 161 gbb0/io56rsb0 162 gnd 163 gbc1/io55rsb0 164 gbc0/io54rsb0 165 io52rsb0 166 io50rsb0 167 io48rsb0 168 io46rsb0 169 io44rsb0 170 v cci b0 171 v cc 172 io36rsb0 173 io35rsb0 174 io34rsb0 175 io33rsb0 176 io32rsb0 177 io31rsb0 178 gnd 179 io29rsb0 180 io28rsb0 181 io27rsb0 182 io26rsb0 183 io25rsb0 184 io24rsb0 185 io23rsb0 186 v cci b0 187 v cc 188 io20rsb0 189 io19rsb0 190 io18rsb0 208-pin pqfp* pin number a3p600 function 191 io17rsb0 192 io16rsb0 193 io14rsb0 194 io12rsb0 195 gnd 196 io10rsb0 197 io09rsb0 198 io08rsb0 199 io07rsb0 200 v cci b0 201 gac1/io05rsb0 202 gac0/io04rsb0 203 gab1/io03rsb0 204 gab0/io02rsb0 205 gaa1/io01rsb0 206 gaa0/io00rsb0 207 gndq 208 vmv0 208-pin pqfp* pin number a3p600 function note: *refer to the "user i/o naming convention" section on page 2-44 .
proasic3 flash family fpgas 4-20 advanced v0.2 208-pin pqfp* pin number a3p1000 function 1gnd 2 gaa2/io219pdb3 3 io219ndb3 4 gab2/io218pdb3 5 io218ndb3 6 gac2/io217pdb3 7 io217ndb3 8 io216pdb3 9 io216ndb3 10 io215pdb3 11 io215ndb3 12 io214pdb3 13 io214ndb3 14 io213pdb3 15 io213ndb3 16 v cc 17 gnd 18 v cci b3 19 io211pdb3 20 io211ndb3 21 gfc1/io206pdb3 22 gfc0/io206ndb3 23 gfb1/io205pdb3 24 gfb0/io205ndb3 25 v complf 26 gfa0/io204npb3 27 v ccplf 28 gfa1/io204ppb3 29 gnd 30 gfa2/io203pdb3 31 io203ndb3 32 gfb2/io202pdb3 33 io202ndb3 34 gfc2/io201pdb3 35 io201ndb3 36 v cc 37 io191pdb3 38 io191ndb3 39 io189psb3 40 v cci b3 41 gnd 42 io188pdb3 43 io188ndb3 44 gec1/io187pdb3 45 gec0/io187ndb3 46 geb1/io186pdb3 47 geb0/io186ndb3 48 gea1/io185pdb3 49 gea0/io185ndb3 50 vmv3 51 gndq 52 gnd 53 nc 54 gea2/io184rsb2 55 geb2/io183rsb2 56 gec2/io182rsb2 57 io181rsb2 58 io180rsb2 59 io179rsb2 60 io178rsb2 61 io177rsb2 62 v cci b2 63 io175rsb2 64 io173rsb2 65 gnd 66 io171rsb2 67 io169rsb2 68 io167rsb2 69 io165rsb2 70 io163rsb2 71 v cc 72 v cci b2 73 io159rsb2 74 io157rsb2 75 io155rsb2 76 io153rsb2 208-pin pqfp* pin number a3p1000 function 77 io151rsb2 78 io149rsb2 79 io147rsb2 80 io145rsb2 81 gnd 82 io140rsb2 83 io138rsb2 84 io136rsb2 85 io134rsb2 86 io132rsb2 87 io130rsb2 88 v cc 89 v cci b2 90 io125rsb2 91 io123rsb2 92 io121rsb2 93 io119rsb2 94 io117rsb2 95 io115rsb2 96 gdc2/io113rsb2 97 gnd 98 gdb2/io112rsb2 99 gda2/io111rsb2 100 gndq 101 tck 102 tdi 103 tms 104 vmv2 105 gnd 106 v pump 107 gndq 108 tdo 109 trst 110 v jtag 111 gda0/io110ndb1 112 gda1/io110pdb1 113 gdb0/io109ndb1 114 gdb1/io109pdb1 208-pin pqfp* pin number a3p1000 function note: *refer to the "user i/o naming convention" section on page 2-44 .
proasic3 flash family fpgas advanced v0.2 4-21 115 gdc0/io108ndb1 116 gdc1/io108pdb1 117 io106ndb1 118 io106pdb1 119 io104ndb1 120 io104pdb1 121 io102psb1 122 gnd 123 v cci b1 124 io97ndb1 125 io97pdb1 126 nc 127 io93ndb1 128 gcc2/io93pdb1 129 gcb2/io92psb1 130 gnd 131 gca2/io91psb1 132 gca1/io90pdb1 133 gca0/io90ndb1 134 gcb0/io89ndb1 135 gcb1/io89pdb1 136 gcc0/io88ndb1 137 gcc1/io88pdb1 138 io85ndb1 139 io85pdb1 140 v cci b1 141 gnd 142 v cc 143 io83psb1 144 io82ndb1 145 io82pdb1 146 io81ndb1 147 io81pdb1 148 io80ndb1 149 gbc2/io80pdb1 150 io79ndb1 151 gbb2/io79pdb1 152 io78ndb1 208-pin pqfp* pin number a3p1000 function 153 gba2/io78pdb1 154 vmv1 155 gndq 156 gnd 157 nc 158 gba1/io77rsb0 159 gba0/io76rsb0 160 gbb1/io75rsb0 161 gbb0/io74rsb0 162 gnd 163 gbc1/io73rsb0 164 gbc0/io72rsb0 165 io70rsb0 166 io67rsb0 167 io63rsb0 168 io60rsb0 169 io57rsb0 170 v cci b0 171 v cc 172 io54rsb0 173 io51rsb0 174 io48rsb0 175 io45rsb0 176 io42rsb0 177 io40rsb0 178 gnd 179 io38rsb0 180 io35rsb0 181 io33rsb0 182 io31rsb0 183 io29rsb0 184 io27rsb0 185 io25rsb0 186 v cci b0 187 v cc 188 io22rsb0 189 io20rsb0 190 io18rsb0 208-pin pqfp* pin number a3p1000 function 191 io16rsb0 192 io15rsb0 193 io14rsb0 194 io13rsb0 195 gnd 196 io12rsb0 197 io11rsb0 198 io10rsb0 199 io09rsb0 200 v cci b0 201 gac1/io05rsb0 202 gac0/io04rsb0 203 gab1/io03rsb0 204 gab0/io02rsb0 205 gaa1/io01rsb0 206 gaa0/io00rsb0 207 gndq 208 vmv0 208-pin pqfp* pin number a3p1000 function note: *refer to the "user i/o naming convention" section on page 2-44 .
proasic3 flash family fpgas 4-22 advanced v0.2 144-pin fbga note for package manufacturing and environmental information, visit resource center at http://www.actel.com/products/ rescenter/package/index.html . 1 2 3 4 5 6 7 8 9 10 11 12 a b c d e f g h j k l m a1 ball pad corner
proasic3 flash family fpgas advanced v0.2 4-23 144-pin fbga* pin number A3P060 function a1 gndq a2 vmv0 a3 gab0/io04rsb0 a4 gab1/io05rsb0 a5 io08rsb0 a6 gnd a7 io11rsb0 a8 v cc a9 io16rsb0 a10 gba0/io23rsb0 a11 gba1/io24rsb0 a12 gndq b1 gab2/io53rsb1 b2 gnd b3 gaa0/io02rsb0 b4 gaa1/io03rsb0 b5 io00rsb0 b6 io10rsb0 b7 io12rsb0 b8 io14rsb0 b9 gbb0/io21rsb0 b10 gbb1/io22rsb0 b11 gnd b12 vmv0 c1 io95rsb1 c2 gfa2/io83rsb1 c3 gac2/io94rsb1 c4 v cc c5 io01rsb0 c6 io09rsb0 c7 io13rsb0 c8 io15rsb0 c9 io17rsb0 c10 gba2/io25rsb0 c11 io26rsb0 c12 gbc2/io29rsb0 d1 io91rsb1 d2 io92rsb1 d3 io93rsb1 d4 gaa2/io51rsb1 d5 gac0/io06rsb0 d6 gac1/io07rsb0 d7 gbc0/io19rsb0 d8 gbc1/io20rsb0 d9 gbb2/io27rsb0 d10 io18rsb0 d11 io28rsb0 d12 gcb1/io37rsb0 e1 v cc e2 gfc0/io88rsb1 e3 gfc1/io89rsb1 e4 v cci b1 e5 io52rsb1 e6 v cci b0 e7 v cci b0 e8 gcc1/io35rsb0 e9 v cci b0 e10 v cc e11 gca0/io40rsb0 e12 io30rsb0 f1 gfb0/io86rsb1 f2 v complf f3 gfb1/io87rsb1 f4 io90rsb1 f5 gnd f6 gnd f7 gnd f8 gcc0/io36rsb0 f9 gcb0/io38rsb0 f10 gnd f11 gca1/io39rsb0 f12 gca2/io41rsb0 144-pin fbga* pin number A3P060 function g1 gfa1/io84rsb1 g2 gnd g3 v ccplf g4 gfa0/io85rsb1 g5 gnd g6 gnd g7 gnd g8 gdc1/io45rsb0 g9 io32rsb0 g10 gcc2/io43rsb0 g11 io31rsb0 g12 gcb2/io42rsb0 h1 v cc h2 gfb2/io82rsb1 h3 gfc2/io81rsb1 h4 gec1/io77rsb1 h5 v cc h6 io34rsb0 h7 io44rsb0 h8 gdb2/io56rsb1 h9 gdc0/io46rsb0 h10 v cci b0 h11 io33rsb0 h12 v cc j1 geb1/io75rsb1 j2 io78rsb1 j3 v cci b1 j4 gec0/io76rsb1 j5 io79rsb1 j6 io80rsb1 j7 v cc j8 tck j9 gda2/io55rsb1 j10 tdo j11 gda1/io49rsb0 j12 gdb1/io47rsb0 144-pin fbga* pin number A3P060 function note: *refer to the "user i/o naming convention" section on page 2-44 .
proasic3 flash family fpgas 4-24 advanced v0.2 k1 geb0/io74rsb1 k2 gea1/io73rsb1 k3 gea0/io72rsb1 k4 gea2/io71rsb1 k5 io65rsb1 k6 io64rsb1 k7 gnd k8 io54rsb1 k9 gdc2/io57rsb1 k10 gnd k11 gda0/io50rsb0 k12 gdb0/io48rsb0 l1 gnd l2 vmv1 l3 geb2/io70rsb1 l4 io67rsb1 l5 v cci b1 l6 io62rsb1 l7 io59rsb1 l8 io58rsb1 l9 tms l10 v jtag l11 vmv1 l12 trst m1 gndq m2 gec2/io69rsb1 m3 io68rsb1 m4 io66rsb1 m5 io63rsb1 m6 io61rsb1 m7 io60rsb1 m8 nc m9 tdi m10 v cci b1 m11 v pump m12 gndq 144-pin fbga* pin number A3P060 function note: *refer to the "user i/o naming convention" section on page 2-44 .
proasic3 flash family fpgas advanced v0.2 4-25 144-pin fbga* pin number a3p250 function a1 gndq a2 vmv0 a3 gab0/io02rsb0 a4 gab1/io03rsb0 a5 io16rsb0 a6 gnd a7 io29rsb0 a8 v cc a9 io33rsb0 a10 gba0/io39rsb0 a11 gba1/io40rsb0 a12 gndq b1 gab2/io117pdb3 b2 gnd b3 gaa0/io00rsb0 b4 gaa1/io01rsb0 b5 io14rsb0 b6 io19rsb0 b7 io22rsb0 b8 io30rsb0 b9 gbb0/io37rsb0 b10 gbb1/io38rsb0 b11 gnd b12 vmv1 c1 io117ndb3 c2 gfa2/io107ppb3 c3 gac2/io116pdb3 c4 v cc c5 io12rsb0 c6 io17rsb0 c7 io24rsb0 c8 io31rsb0 c9 io34rsb0 c10 gba2/io41pdb1 c11 io41ndb1 c12 gbc2/io43ppb1 d1 io112ndb3 d2 io112pdb3 d3 io116ndb3 d4 gaa2/io118ppb3 d5 gac0/io04rsb0 d6 gac1/io05rsb0 d7 gbc0/io35rsb0 d8 gbc1/io36rsb0 d9 gbb2/io42pdb1 d10 io42ndb1 d11 io43npb1 d12 gcb1/io49ppb1 e1 v cc e2 gfc0/io110ndb3 e3 gfc1/io110pdb3 e4 v cci b3 e5 io118npb3 e6 v cci b0 e7 v cci b0 e8 gcc1/io48pdb1 e9 v cci b1 e10 v cc e11 gca0/io50ndb1 e12 io51ndb1 f1 gfb0/io109npb3 f2 v complf f3 gfb1/io109ppb3 f4 io107npb3 f5 gnd f6 gnd f7 gnd f8 gcc0/io48ndb1 f9 gcb0/io49npb1 f10 gnd f11 gca1/io50pdb1 f12 gca2/io51pdb1 144-pin fbga* pin number a3p250 function g1 gfa1/io108ppb3 g2 gnd g3 v ccplf g4 gfa0/io108npb3 g5 gnd g6 gnd g7 gnd g8 gdc1/io58ppb1 g9 io53ndb1 g10 gcc2/io53pdb1 g11 io52ndb1 g12 gcb2/io52pdb1 h1 v cc h2 gfb2/io106pdb3 h3 gfc2/io105psb3 h4 gec1/io100pdb3 h5 v cc h6 io79rsb2 h7 io65rsb2 h8 gdb2/io62rsb2 h9 gdc0/io58npb1 h10 v cci b1 h11 io54psb1 h12 v cc j1 geb1/io99pdb3 j2 io106ndb3 j3 v cci b3 j4 gec0/io100ndb3 j5 io88rsb2 j6 io81rsb2 j7 v cc j8 tck j9 gda2/io61rsb2 j10 tdo j11 gda1/io60pdb1 j12 gdb1/io59pdb1 144-pin fbga* pin number a3p250 function note: *refer to the "user i/o naming convention" section on page 2-44 .
proasic3 flash family fpgas 4-26 advanced v0.2 k1 geb0/io99ndb3 k2 gea1/io98pdb3 k3 gea0/io98ndb3 k4 gea2/io97rsb2 k5 io90rsb2 k6 io84rsb2 k7 gnd k8 io66rsb2 k9 gdc2/io63rsb2 k10 gnd k11 gda0/io60ndb1 k12 gdb0/io59ndb1 l1 gnd l2 vmv3 l3 geb2/io96rsb2 l4 io91rsb2 l5 v cci b2 l6 io82rsb2 l7 io80rsb2 l8 io72rsb2 l9 tms l10 v jtag l11 vmv2 l12 trst m1 gndq m2 gec2/io95rsb2 m3 io92rsb2 m4 io89rsb2 m5 io87rsb2 m6 io85rsb2 m7 io78rsb2 m8 io76rsb2 m9 tdi m10 v cci b2 m11 v pump m12 gndq 144-pin fbga* pin number a3p250 function note: *refer to the "user i/o naming convention" section on page 2-44 .
proasic3 flash family fpgas advanced v0.2 4-27 256-pin fbga note for package manufacturing and environmental information, visit resource center at http://www.actel.com/products/ rescenter/package/index.html . 1 3 5 7 9 11 13 15 2 4 6 8 10 12 14 16 c e g j l n r d f h k m p t b a a1 ball pad corner
proasic3 flash family fpgas 4-28 advanced v0.2 256-pin fbga* pin number a3p250 function a1 gnd a2 gaa0/io00rsb0 a3 gaa1/io01rsb0 a4 gab0/io02rsb0 a5 io07rsb0 a6 io10rsb0 a7 io11rsb0 a8 io15rsb0 a9 io20rsb0 a10 io25rsb0 a11 io29rsb0 a12 io33rsb0 a13 gbb1/io38rsb0 a14 gba0/io39rsb0 a15 gba1/io40rsb0 a16 gnd b1 gab2/io117pdb3 b2 gaa2/io118pdb3 b3 nc b4 gab1/io03rsb0 b5 io06rsb0 b6 io09rsb0 b7 io12rsb0 b8 io16rsb0 b9 io21rsb0 b10 io26rsb0 b11 io30rsb0 b12 gbc1/io36rsb0 b13 gbb0/io37rsb0 b14 nc b15 gba2/io41pdb1 b16 io41ndb1 c1 io117ndb3 c2 io118ndb3 c3 nc c4 nc c5 gac0/io04rsb0 c6 gac1/io05rsb0 c7 io13rsb0 c8 io17rsb0 c9 io22rsb0 c10 io27rsb0 c11 io31rsb0 c12 gbc0/io35rsb0 c13 io34rsb0 c14 nc c15 io42npb1 c16 io44pdb1 d1 io114ndb3 d2 io114pdb3 d3 gac2/io116pdb3 d4 nc d5 gndq d6 io08rsb0 d7 io14rsb0 d8 io18rsb0 d9 io23rsb0 d10 io28rsb0 d11 io32rsb0 d12 gndq d13 nc d14 gbb2/io42ppb1 d15 nc d16 io44ndb1 e1 io113pdb3 e2 nc e3 io116ndb3 e4 io115pdb3 e5 vmv0 e6 v cci b0 e7 v cci b0 e8 io19rsb0 e9 io24rsb0 e10 v cci b0 256-pin fbga* pin number a3p250 function e11 v cci b0 e12 vmv1 e13 gbc2/io43pdb1 e14 io46rsb1 e15 nc e16 io45pdb1 f1 io113ndb3 f2 io112ppb3 f3 nc f4 io115ndb3 f5 v cci b3 f6 gnd f7 v cc f8 v cc f9 v cc f10 v cc f11 gnd f12 v cci b1 f13 io43ndb1 f14 nc f15 io47ppb1 f16 io45ndb1 g1 io111ndb3 g2 io111pdb3 g3 io112npb3 g4 gfc1/io110ppb3 g5 v cci b3 g6 v cc g7 gnd g8 gnd g9 gnd g10 gnd g11 v cc g12 v cci b1 g13 gcc1/io48ppb1 g14 io47npb1 g15 io54pdb1 256-pin fbga* pin number a3p250 function note: *refer to the "user i/o naming convention" section on page 2-44 .
proasic3 flash family fpgas advanced v0.2 4-29 g16 io54ndb1 h1 gfb0/io109npb3 h2 gfa0/io108ndb3 h3 gfb1/io109ppb3 h4 v complf h5 gfc0/io110npb3 h6 v cc h7 gnd h8 gnd h9 gnd h10 gnd h11 v cc h12 gcc0/io48npb1 h13 gcb1/io49ppb1 h14 gca0/io50npb1 h15 nc h16 gcb0/io49npb1 j1 gfa2/io107ppb3 j2 gfa1/io108pdb3 j3 v ccplf j4 io106ndb3 j5 gfb2/io106pdb3 j6 v cc j7 gnd j8 gnd j9 gnd j10 gnd j11 v cc j12 gcb2/io52ppb1 j13 gca1/io50ppb1 j14 gcc2/io53ppb1 j15 nc j16 gca2/io51pdb1 k1 gfc2/io105pdb3 k2 io107npb3 k3 io104ppb3 k4 nc 256-pin fbga* pin number a3p250 function k5 v cci b3 k6 v cc k7 gnd k8 gnd k9 gnd k10 gnd k11 v cc k12 v cci b1 k13 io52npb1 k14 io55rsb1 k15 io53npb1 k16 io51ndb1 l1 io105ndb3 l2 io104npb3 l3 nc l4 io102rsb3 l5 v cci b3 l6 gnd l7 v cc l8 v cc l9 v cc l10 v cc l11 gnd l12 v cci b1 l13 gdb0/io59npb1 l14 io57ndb1 l15 io57pdb1 l16 io56pdb1 m1 io103pdb3 m2 nc m3 io101npb3 m4 gec0/io100npb3 m5 vmv3 m6 v cci b2 m7 v cci b2 m8 nc m9 io74rsb2 256-pin fbga* pin number a3p250 function m10 v cci b2 m11 v cci b2 m12 vmv2 m13 nc m14 gdb1/io59ppb1 m15 gdc1/io58pdb1 m16 io56ndb1 n1 io103ndb3 n2 io101ppb3 n3 gec1/io100ppb3 n4 nc n5 gndq n6 gea2/io97rsb2 n7 io86rsb2 n8 io82rsb2 n9 io75rsb2 n10 io69rsb2 n11 io64rsb2 n12 gndq n13 nc n14 v jtag n15 gdc0/io58ndb1 n16 gda1/io60pdb1 p1 geb1/io99pdb3 p2 geb0/io99ndb3 p3 nc p4 nc p5 io92rsb2 p6 io89rsb2 p7 io85rsb2 p8 io81rsb2 p9 io76rsb2 p10 io71rsb2 p11 io66rsb2 p12 nc p13 tck p14 v pump 256-pin fbga* pin number a3p250 function note: *refer to the "user i/o naming convention" section on page 2-44 .
proasic3 flash family fpgas 4-30 advanced v0.2 p15 trst p16 gda0/io60ndb1 r1 gea1/io98pdb3 r2 gea0/io98ndb3 r3 nc r4 gec2/io95rsb2 r5 io91rsb2 r6 io88rsb2 r7 io84rsb2 r8 io80rsb2 r9 io77rsb2 r10 io72rsb2 r11 io68rsb2 r12 io65rsb2 r13 gdb2/io62rsb2 r14 tdi r15 nc r16 tdo t1 gnd t2 io94rsb2 t3 geb2/io96rsb2 t4 io93rsb2 t5 io90rsb2 t6 io87rsb2 t7 io83rsb2 t8 io79rsb2 t9 io78rsb2 t10 io73rsb2 t11 io70rsb2 t12 gdc2/io63rsb2 t13 io67rsb2 t14 gda2/io61rsb2 t15 tms t16 gnd 256-pin fbga* pin number a3p250 function note: *refer to the "user i/o naming convention" section on page 2-44 .
proasic3 flash family fpgas advanced v0.2 4-31 256-pin fbga* pin number a3p400 function a1 gnd a2 gaa0/io00rsb0 a3 gaa1/io01rsb0 a4 gab0/io02rsb0 a5 io14rsb0 a6 io18rsb0 a7 io22rsb0 a8 io27rsb0 a9 io30rsb0 a10 io39rsb0 a11 io41rsb0 a12 io46rsb0 a13 gbb1/io57rsb0 a14 gba0/io58rsb0 a15 gba1/io59rsb0 a16 gnd b1 gab2/io154pdb3 b2 gaa2/io155ppb3 b3 io10rsb0 b4 gab1/io03rsb0 b5 io12rsb0 b6 io16rsb0 b7 io21rsb0 b8 io26rsb0 b9 io31rsb0 b10 io37rsb0 b11 io42rsb0 b12 gbc1/io55rsb0 b13 gbb0/io56rsb0 b14 io48rsb0 b15 gba2/io60ppb1 b16 io50rsb0 c1 io154ndb3 c2 io08rsb0 c3 io07rsb0 c4 io06rsb0 c5 gac0/io04rsb0 c6 gac1/io05rsb0 c7 io20rsb0 c8 io25rsb0 c9 io32rsb0 c10 io38rsb0 c11 io44rsb0 c12 gbc0/io54rsb0 c13 io51rsb0 c14 io52rsb0 c15 io53rsb0 c16 io60npb1 d1 io152npb3 d2 io155npb3 d3 gac2/io153pdb3 d4 io09rsb0 d5 gndq d6 io15rsb0 d7 io19rsb0 d8 io24rsb0 d9 io33rsb0 d10 io40rsb0 d11 io43rsb0 d12 gndq d13 io49rsb0 d14 gbb2/io61pdb1 d15 io63ndb1 d16 io64ndb1 e1 io151pdb3 e2 io152ppb3 e3 io153ndb3 e4 io11rsb0 e5 vmv0 e6 v cci b0 e7 v cci b0 e8 io28rsb0 e9 io35rsb0 e10 v cci b0 256-pin fbga* pin number a3p400 function e11 v cci b0 e12 vmv1 e13 gbc2/io62pdb1 e14 io61ndb1 e15 io63pdb1 e16 io64pdb1 f1 io151ndb3 f2 io150ppb3 f3 nc f4 io148ppb3 f5 v cci b3 f6 gnd f7 v cc f8 v cc f9 v cc f10 v cc f11 gnd f12 v cci b1 f13 io62ndb1 f14 nc f15 io65rsb1 f16 io73ndb1 g1 io150npb3 g2 io149pdb3 g3 io149ndb3 g4 gfc1/io147ppb3 g5 v cci b3 g6 v cc g7 gnd g8 gnd g9 gnd g10 gnd g11 v cc g12 v cci b1 g13 gcc1/io67ppb1 g14 io66ndb1 g15 io66pdb1 256-pin fbga* pin number a3p400 function note: *refer to the "user i/o naming convention" section on page 2-44 .
proasic3 flash family fpgas 4-32 advanced v0.2 g16 io73pdb1 h1 gfb0/io146npb3 h2 gfa0/io145ndb3 h3 gfb1/io146ppb3 h4 v complf h5 gfc0/io147npb3 h6 v cc h7 gnd h8 gnd h9 gnd h10 gnd h11 v cc h12 gcc0/io67npb1 h13 gcb1/io68ppb1 h14 gca0/io69npb1 h15 nc h16 gcb0/io68npb1 j1 gfa2/io144ppb3 j2 gfa1/io145pdb3 j3 v ccplf j4 io148npb3 j5 gfb2/io143ppb3 j6 v cc j7 gnd j8 gnd j9 gnd j10 gnd j11 v cc j12 gcb2/io71ppb1 j13 gca1/io69ppb1 j14 gcc2/io72pdb1 j15 nc j16 gca2/io70pdb1 k1 gfc2/io142pdb3 k2 io144npb3 k3 io143npb3 k4 io138pdb3 256-pin fbga* pin number a3p400 function k5 v cci b3 k6 v cc k7 gnd k8 gnd k9 gnd k10 gnd k11 v cc k12 v cci b1 k13 io71npb1 k14 io72ndb1 k15 io74rsb1 k16 io70ndb1 l1 io142ndb3 l2 io140ndb3 l3 io139rsb3 l4 io138ndb3 l5 v cci b3 l6 gnd l7 v cc l8 v cc l9 v cc l10 v cc l11 gnd l12 v cci b0 l13 gdb0/io78npb1 l14 io75ndb1 l15 io75pdb1 l16 io76pdb1 m1 io141ndb3 m2 io140pdb3 m3 io127rsb2 m4 gec0/io137npb3 m5 vmv3 m6 v cci b2 m7 v cci b2 m8 io106rsb2 m9 io99rsb2 256-pin fbga* pin number a3p400 function m10 v cci b2 m11 v cci b2 m12 vmv2 m13 io85rsb2 m14 gdb1/io78ppb1 m15 gdc1/io77pdb1 m16 io76ndb1 n1 io141pdb3 n2 io131rsb2 n3 gec1/io137ppb3 n4 io128rsb2 n5 gndq n6 gea2/io134rsb2 n7 io113rsb2 n8 io109rsb2 n9 io100rsb2 n10 io95rsb2 n11 io90rsb2 n12 gndq n13 io83rsb2 n14 v jtag n15 gdc0/io77ndb1 n16 gda1/io79pdb1 p1 geb1/io136pdb3 p2 geb0/io136ndb3 p3 io130rsb2 p4 io129rsb2 p5 io126rsb2 p6 io121rsb2 p7 io115rsb2 p8 io108rsb2 p9 io101rsb2 p10 io94rsb2 p11 io88rsb2 p12 io84rsb2 p13 tck p14 v pump 256-pin fbga* pin number a3p400 function note: *refer to the "user i/o naming convention" section on page 2-44 .
proasic3 flash family fpgas advanced v0.2 4-33 p15 trst p16 gda0/io79ndb1 r1 gea1/io135pdb3 r2 gea0/io135ndb3 r3 io125rsb2 r4 gec2/io132rsb2 r5 io122rsb2 r6 io118rsb2 r7 io112rsb2 r8 io107rsb2 r9 io102rsb2 r10 io96rsb2 r11 io91rsb2 r12 io87rsb2 r13 gdb2/io81rsb2 r14 tdi r15 nc r16 tdo t1 gnd t2 io124rsb2 t3 geb2/io133rsb2 t4 io123rsb2 t5 io120rsb2 t6 io116rsb2 t7 io111rsb2 t8 io105rsb2 t9 io103rsb2 t10 io97rsb2 t11 io93rsb2 t12 gdc2/io82rsb2 t13 io86rsb2 t14 gda2/io80rsb2 t15 tms t16 gnd 256-pin fbga* pin number a3p400 function note: *refer to the "user i/o naming convention" section on page 2-44 .
proasic3 flash family fpgas 4-34 advanced v0.2 256-pin fbga* pin number a3p600 function a1 gnd a2 gaa0/io00rsb0 a3 gaa1/io01rsb0 a4 gab0/io02rsb0 a5 io12rsb0 a6 io14rsb0 a7 io19rsb0 a8 io26rsb0 a9 io31rsb0 a10 io37rsb0 a11 io41rsb0 a12 io47rsb0 a13 gbb1/io57rsb0 a14 gba0/io58rsb0 a15 gba1/io59rsb0 a16 gnd b1 gab2/io169pdb3 b2 gaa2/io170pdb3 b3 gndq b4 gab1/io03rsb0 b5 io10rsb0 b6 io15rsb0 b7 io18rsb0 b8 io24rsb0 b9 io32rsb0 b10 io40rsb0 b11 io43rsb0 b12 gbc1/io55rsb0 b13 gbb0/io56rsb0 b14 io49rsb0 b15 gba2/io60pdb1 b16 io60ndb1 c1 io169ndb3 c2 io170ndb3 c3 vmv3 c4 io06rsb0 c5 gac0/io04rsb0 c6 gac1/io05rsb0 c7 io17rsb0 c8 io25rsb0 c9 io33rsb0 c10 io38rsb0 c11 io42rsb0 c12 gbc0/io54rsb0 c13 io52rsb0 c14 io51rsb0 c15 io50rsb0 c16 io61npb1 d1 io166ndb3 d2 io166pdb3 d3 gac2/io168pdb3 d4 io168ndb3 d5 gndq d6 io13rsb0 d7 io16rsb0 d8 io22rsb0 d9 io36rsb0 d10 io39rsb0 d11 io46rsb0 d12 gndq d13 io53rsb0 d14 gbb2/io61ppb1 d15 io63ppb1 d16 io65pdb1 e1 io165ndb3 e2 io165pdb3 e3 io167pdb3 e4 io167ndb3 e5 vmv0 e6 v cci b0 e7 v cci b0 e8 io29rsb0 e9 io30rsb0 e10 v cci b0 256-pin fbga* pin number a3p600 function e11 v cci b0 e12 vmv1 e13 gbc2/io62pdb1 e14 io63npb1 e15 io64ppb1 e16 io65ndb1 f1 io154psb3 f2 io162ppb3 f3 io164pdb3 f4 io164ndb3 f5 v cci b3 f6 gnd f7 v cc f8 v cc f9 v cc f10 v cc f11 gnd f12 v cci b1 f13 io62ndb1 f14 io64npb1 f15 io66ppb1 f16 io67ppb1 g1 io155ndb3 g2 io155pdb3 g3 io162npb3 g4 gfc1/io161ppb3 g5 v cci b3 g6 v cc g7 gnd g8 gnd g9 gnd g10 gnd g11 v cc g12 v cci b1 g13 gcc1/io68ppb1 g14 io66npb1 g15 io67npb1 256-pin fbga* pin number a3p600 function note: *refer to the "user i/o naming convention" section on page 2-44 .
proasic3 flash family fpgas advanced v0.2 4-35 g16 io71npb1 h1 gfb0/io160npb3 h2 gfa0/io159ndb3 h3 gfb1/io160ppb3 h4 v complf h5 gfc0/io161npb3 h6 v cc h7 gnd h8 gnd h9 gnd h10 gnd h11 v cc h12 gcc0/io68npb1 h13 gcb1/io69ppb1 h14 gca0/io70npb1 h15 io73npb1 h16 gcb0/io69npb1 j1 gfa2/io158ppb3 j2 gfa1/io159pdb3 j3 v ccplf j4 io157ndb3 j5 gfb2/io157pdb3 j6 v cc j7 gnd j8 gnd j9 gnd j10 gnd j11 v cc j12 gcb2/io72ppb1 j13 gca1/io70ppb1 j14 gcc2/io73ppb1 j15 io77ppb1 j16 gca2/io71ppb1 k1 gfc2/io156ppb3 k2 io158npb3 k3 io151pdb3 k4 io151ndb3 256-pin fbga* pin number a3p600 function k5 v cci b3 k6 v cc k7 gnd k8 gnd k9 gnd k10 gnd k11 v cc k12 v cci b1 k13 io72npb1 k14 io82pdb1 k15 io79pdb1 k16 io77npb1 l1 io149pdb3 l2 io156npb3 l3 io147pdb3 l4 io147ndb3 l5 v cci b3 l6 gnd l7 v cc l8 v cc l9 v cc l10 v cc l11 gnd l12 v cci b1 l13 gdb0/io85npb1 l14 io82ndb1 l15 io79ndb1 l16 io80pdb1 m1 io149ndb3 m2 io146pdb3 m3 io146ndb3 m4 gec0/io144npb3 m5 vmv3 m6 v cci b2 m7 v cci b2 m8 io111rsb2 m9 io110rsb2 256-pin fbga* pin number a3p600 function m10 v cci b2 m11 v cci b2 m12 vmv2 m13 io81ndb1 m14 gdb1/io85ppb1 m15 gdc1/io84pdb1 m16 io80ndb1 n1 io145pdb3 n2 io145ndb3 n3 gec1/io144ppb3 n4 io137rsb2 n5 gndq n6 gea2/io141rsb2 n7 io120rsb2 n8 io113rsb2 n9 io106rsb2 n10 io99rsb2 n11 io94rsb2 n12 gndq n13 io81pdb1 n14 v jtag n15 gdc0/io84ndb1 n16 gda1/io86pdb1 p1 geb1/io143pdb3 p2 geb0/io143ndb3 p3 io138rsb2 p4 io135rsb2 p5 io134rsb2 p6 io128rsb2 p7 io121rsb2 p8 io115rsb2 p9 io108rsb2 p10 io100rsb2 p11 io95rsb2 p12 vmv1 p13 tck p14 v pump 256-pin fbga* pin number a3p600 function note: *refer to the "user i/o naming convention" section on page 2-44 .
proasic3 flash family fpgas 4-36 advanced v0.2 p15 trst p16 gda0/io86ndb1 r1 gea1/io142pdb3 r2 gea0/io142ndb3 r3 io136rsb2 r4 gec2/io139rsb2 r5 io130rsb2 r6 io125rsb2 r7 io119rsb2 r8 io114rsb2 r9 io107rsb2 r10 io101rsb2 r11 io96rsb2 r12 io90rsb2 r13 gdb2/io88rsb2 r14 tdi r15 gndq r16 tdo t1 gnd t2 io133rsb2 t3 geb2/io140rsb2 t4 io132rsb2 t5 io127rsb2 t6 io123rsb2 t7 io117rsb2 t8 io112rsb2 t9 io109rsb2 t10 io102rsb2 t11 io97rsb2 t12 gdc2/io89rsb2 t13 io91rsb2 t14 gda2/io87rsb2 t15 tms t16 gnd 256-pin fbga* pin number a3p600 function note: *refer to the "user i/o naming convention" section on page 2-44 .
proasic3 flash family fpgas advanced v0.2 4-37 256-pin fbga* pin number a3p1000 function a1 gnd a2 gaa0/io00rsb0 a3 gaa1/io01rsb0 a4 gab0/io02rsb0 a5 io17rsb0 a6 io22rsb0 a7 io28rsb0 a8 io34rsb0 a9 io44rsb0 a10 io50rsb0 a11 io56rsb0 a12 io62rsb0 a13 gbb1/io75rsb0 a14 gba0/io76rsb0 a15 gba1/io77rsb0 a16 gnd b1 gab2/io218pdb3 b2 gaa2/io219pdb3 b3 gndq b4 gab1/io03rsb0 b5 io15rsb0 b6 io20rsb0 b7 io26rsb0 b8 io35rsb0 b9 io45rsb0 b10 io52rsb0 b11 io57rsb0 b12 gbc1/io73rsb0 b13 gbb0/io74rsb0 b14 io69rsb0 b15 gba2/io78pdb1 b16 io78ndb1 c1 io218ndb3 c2 io219ndb3 c3 vmv3 c4 io06rsb0 c5 gac0/io04rsb0 c6 gac1/io05rsb0 c7 io27rsb0 c8 io33rsb0 c9 io43rsb0 c10 io51rsb0 c11 io58rsb0 c12 gbc0/io72rsb0 c13 io70rsb0 c14 io71rsb0 c15 io81pdb1 c16 io81ndb1 d1 io215ndb3 d2 io215pdb3 d3 gac2/io217pdb3 d4 io217ndb3 d5 gndq d6 io21rsb0 d7 io25rsb0 d8 io31rsb0 d9 io46rsb0 d10 io53rsb0 d11 io59rsb0 d12 gndq d13 io80ndb1 d14 gbb2/io79pdb1 d15 io82pdb1 d16 io82ndb1 e1 io210pdb3 e2 io213ndb3 e3 io213pdb3 e4 io216pdb3 e5 vmv0 e6 v cci b0 e7 v cci b0 e8 io38rsb0 e9 io47rsb0 e10 v cci b0 256-pin fbga* pin number a3p1000 function e11 v cci b0 e12 vmv1 e13 gbc2/io80pdb1 e14 io79ndb1 e15 io83pdb1 e16 io83ndb1 f1 io210ndb3 f2 io211ndb3 f3 io211pdb3 f4 io216ndb3 f5 v cci b3 f6 gnd f7 v cc f8 v cc f9 v cc f10 v cc f11 gnd f12 v cci b1 f13 io85pdb1 f14 io85ndb1 f15 io86pdb1 f16 io86ndb1 g1 io200psb3 g2 io208ndb3 g3 io208pdb3 g4 gfc1/io206ppb3 g5 v cci b3 g6 v cc g7 gnd g8 gnd g9 gnd g10 gnd g11 v cc g12 v cci b1 g13 gcc1/io88ppb1 g14 io87pdb1 g15 io87ndb1 256-pin fbga* pin number a3p1000 function note: *refer to the "user i/o naming convention" section on page 2-44 .
proasic3 flash family fpgas 4-38 advanced v0.2 g16 io94psb1 h1 gfb0/io205npb3 h2 gfa0/io204ndb3 h3 gfb1/io205ppb3 h4 v complf h5 gfc0/io206npb3 h6 v cc h7 gnd h8 gnd h9 gnd h10 gnd h11 v cc h12 gcc0/io88npb1 h13 gcb1/io89ppb1 h14 gca0/io90npb1 h15 io91npb1 h16 gcb0/io89npb1 j1 gfa2/io203ppb3 j2 gfa1/io204pdb3 j3 v ccplf j4 io202ndb3 j5 gfb2/io202pdb3 j6 v cc j7 gnd j8 gnd j9 gnd j10 gnd j11 v cc j12 gcb2/io92ppb1 j13 gca1/io90ppb1 j14 gcc2/io93pdb1 j15 io93ndb1 j16 gca2/io91ppb1 k1 gfc2/io201psb3 k2 io203npb3 k3 io197pdb3 k4 io197ndb3 256-pin fbga* pin number a3p1000 function k5 v cci b3 k6 v cc k7 gnd k8 gnd k9 gnd k10 gnd k11 v cc k12 v cci b1 k13 io92npb1 k14 io100ndb1 k15 io100pdb1 k16 io102pdb1 l1 io195pdb3 l2 io195ndb3 l3 io194pdb3 l4 io194ndb3 l5 v cci b3 l6 gnd l7 v cc l8 v cc l9 v cc l10 v cc l11 gnd l12 v cci b1 l13 gdb0/io109npb1 l14 io103ndb1 l15 io103pdb1 l16 io102ndb1 m1 io191pdb3 m2 io190pdb3 m3 io190ndb3 m4 gec0/io187npb3 m5 vmv3 m6 v cci b2 m7 v cci b2 m8 io144rsb2 m9 io133rsb2 256-pin fbga* pin number a3p1000 function m10 v cci b2 m11 v cci b2 m12 vmv2 m13 io107pdb1 m14 gdb1/io109ppb1 m15 gdc1/io108pdb1 m16 io106psb1 n1 io191ndb3 n2 io188ppb3 n3 gec1/io187ppb3 n4 io188npb3 n5 gndq n6 gea2/io184rsb2 n7 io153rsb2 n8 io146rsb2 n9 io134rsb2 n10 io126rsb2 n11 io121rsb2 n12 gndq n13 io107ndb1 n14 v jtag n15 gdc0/io108ndb1 n16 gda1/io110pdb1 p1 geb1/io186pdb3 p2 geb0/io186ndb3 p3 io181rsb2 p4 io178rsb2 p5 io166rsb2 p6 io159rsb2 p7 io154rsb2 p8 io148rsb2 p9 io138rsb2 p10 io131rsb2 p11 io124rsb2 p12 vmv1 p13 tck p14 v pump 256-pin fbga* pin number a3p1000 function note: *refer to the "user i/o naming convention" section on page 2-44 .
proasic3 flash family fpgas advanced v0.2 4-39 p15 trst p16 gda0/io110ndb1 r1 gea1/io185pdb3 r2 gea0/io185ndb3 r3 io177rsb2 r4 gec2/io182rsb2 r5 io167rsb2 r6 io160rsb2 r7 io155rsb2 r8 io150rsb2 r9 io139rsb2 r10 io130rsb2 r11 io127rsb2 r12 io119rsb2 r13 gdb2/io112rsb2 r14 tdi r15 gndq r16 tdo t1 gnd t2 io176rsb2 t3 geb2/io183rsb2 t4 io170rsb2 t5 io164rsb2 t6 io158rsb2 t7 io152rsb2 t8 io145rsb2 t9 io137rsb2 t10 io132rsb2 t11 io125rsb2 t12 gdc2/io113rsb2 t13 io117rsb2 t14 gda2/io111rsb2 t15 tms t16 gnd 256-pin fbga* pin number a3p1000 function note: *refer to the "user i/o naming convention" section on page 2-44 .
proasic3 flash family fpgas 4-40 advanced v0.2 484-pin fbga note for package manufacturing and environmental information, visit resource center at http://www.actel.com/products/ rescenter/package/index.html . a b c d e f g h j k l m n p r t u v w y aa ab 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 a1 ball pad corner
proasic3 flash family fpgas advanced v0.2 4-41 484-pin fbga* pin number a3p400 function a1 gnd a2 gnd a3 v cci b0 a4 nc a5 nc a6 io13rsb0 a7 io17rsb0 a8 nc a9 nc a10 io23rsb0 a11 io29rsb0 a12 io34rsb0 a13 io36rsb0 a14 nc a15 nc a16 io45rsb0 a17 io47rsb0 a18 nc a19 nc a20 v cci b0 a21 gnd a22 gnd b1 gnd b2 v cci b3 b3 nc b4 nc b5 nc b6 nc b7 nc b8 nc b9 nc b10 nc b11 nc b12 nc b13 nc b14 nc b15 nc b16 nc b17 nc b18 nc b19 nc b20 nc b21 v cci b1 b22 gnd c1 v cci b3 c2 nc c3 nc c4 nc c5 gnd c6 nc c7 nc c8 v cc c9 v cc c10 nc c11 nc c12 nc c13 nc c14 v cc c15 v cc c16 nc c17 nc c18 gnd c19 nc c20 nc c21 nc c22 v cci b1 d1 nc d2 nc d3 nc d4 gnd d5 gaa0/io00rsb0 d6 gaa1/io01rsb0 484-pin fbga* pin number a3p400 function d7 gab0/io02rsb0 d8 io14rsb0 d9 io18rsb0 d10 io22rsb0 d11 io27rsb0 d12 io30rsb0 d13 io39rsb0 d14 io41rsb0 d15 io46rsb0 d16 gbb1/io57rsb0 d17 gba0/io58rsb0 d18 gba1/io59rsb0 d19 gnd d20 nc d21 nc d22 nc e1 nc e2 nc e3 gnd e4 gab2/io154pdb3 e5 gaa2/io155ppb3 e6 io10rsb0 e7 gab1/io03rsb0 e8 io12rsb0 e9 io16rsb0 e10 io21rsb0 e11 io26rsb0 e12 io31rsb0 e13 io37rsb0 e14 io42rsb0 e15 gbc1/io55rsb0 e16 gbb0/io56rsb0 e17 io48rsb0 e18 gba2/io60ppb1 e19 io50rsb0 e20 gnd 484-pin fbga* pin number a3p400 function note: *refer to the "user i/o naming convention" section on page 2-44 .
proasic3 flash family fpgas 4-42 advanced v0.2 e21 nc e22 nc f1 nc f2 nc f3 nc f4 io154ndb3 f5 io08rsb0 f6 io07rsb0 f7 io06rsb0 f8 gac0/io04rsb0 f9 gac1/io05rsb0 f10 io20rsb0 f11 io25rsb0 f12 io32rsb0 f13 io38rsb0 f14 io44rsb0 f15 gbc0/io54rsb0 f16 io51rsb0 f17 io52rsb0 f18 io53rsb0 f19 io60npb1 f20 nc f21 nc f22 nc g1 nc g2 nc g3 nc g4 io152npb3 g5 io155npb3 g6 gac2/io153pdb3 g7 io09rsb0 g8 gndq g9 io15rsb0 g10 io19rsb0 g11 io24rsb0 g12 io33rsb0 484-pin fbga* pin number a3p400 function g13 io40rsb0 g14 io43rsb0 g15 gndq g16 io49rsb0 g17 gbb2/io61pdb1 g18 io63ndb1 g19 io64ndb1 g20 nc g21 nc g22 nc h1 nc h2 nc h3 v cc h4 io151pdb3 h5 io152ppb3 h6 io153ndb3 h7 io11rsb0 h8 vmv0 h9 v cci b0 h10 v cci b0 h11 io28rsb0 h12 io35rsb0 h13 v cci b0 h14 v cci b0 h15 vmv1 h16 gbc2/io62pdb1 h17 io61ndb1 h18 io63pdb1 h19 io64pdb1 h20 v cc h21 nc h22 nc j1 nc j2 nc j3 nc j4 io151ndb3 484-pin fbga* pin number a3p400 function j5 io150ppb3 j6 nc j7 io148ppb3 j8 v cci b3 j9 gnd j10 v cc j11 v cc j12 v cc j13 v cc j14 gnd j15 v cci b1 j16 io62ndb1 j17 nc j18 io65rsb1 j19 io73ndb1 j20 nc j21 nc j22 nc k1 nc k2 nc k3 nc k4 io150npb3 k5 io149pdb3 k6 io149ndb3 k7 gfc1/io147ppb3 k8 v cci b3 k9 v cc k10 gnd k11 gnd k12 gnd k13 gnd k14 v cc k15 v cci b1 k16 gcc1/io67ppb1 k17 io66ndb1 k18 io66pdb1 484-pin fbga* pin number a3p400 function note: *refer to the "user i/o naming convention" section on page 2-44 .
proasic3 flash family fpgas advanced v0.2 4-43 k19 io73pdb1 k20 nc k21 nc k22 nc l1 nc l2 nc l3 nc l4 gfb0/io146npb3 l5 gfa0/io145ndb3 l6 gfb1/io146ppb3 l7 v complf l8 gfc0/io147npb3 l9 v cc l10 gnd l11 gnd l12 gnd l13 gnd l14 v cc l15 gcc0/io67npb1 l16 gcb1/io68ppb1 l17 gca0/io69npb1 l18 nc l19 gcb0/io68npb1 l20 nc l21 nc l22 nc m1 nc m2 nc m3 nc m4 gfa2/io144ppb3 m5 gfa1/io145pdb3 m6 v ccplf m7 io148npb3 m8 gfb2/io143ppb3 m9 v cc m10 gnd 484-pin fbga* pin number a3p400 function m11 gnd m12 gnd m13 gnd m14 v cc m15 gcb2/io71ppb1 m16 gca1/io69ppb1 m17 gcc2/io72pdb1 m18 nc m19 gca2/io70pdb1 m20 nc m21 nc m22 nc n1 nc n2 nc n3 nc n4 gfc2/io142pdb3 n5 io144npb3 n6 io143npb3 n7 io138pdb3 n8 v cci b3 n9 v cc n10 gnd n11 gnd n12 gnd n13 gnd n14 v cc n15 v cci b1 n16 io71npb1 n17 io72ndb1 n18 io74rsb1 n19 io70ndb1 n20 nc n21 nc n22 nc p1 nc p2 nc 484-pin fbga* pin number a3p400 function p3 nc p4 io142ndb3 p5 io140ndb3 p6 io139rsb3 p7 io138ndb3 p8 v cci b3 p9 gnd p10 v cc p11 v cc p12 v cc p13 v cc p14 gnd p15 v cci b1 p16 gdb0/io78npb1 p17 io75ndb1 p18 io75pdb1 p19 io76pdb1 p20 nc p21 nc p22 nc r1 nc r2 nc r3 v cc r4 io141ndb3 r5 io140pdb3 r6 io127rsb2 r7 gec0/io137npb3 r8 vmv3 r9 v cci b2 r10 v cci b2 r11 io106rsb2 r12 io99rsb2 r13 v cci b2 r14 v cci b2 r15 vmv2 r16 io85rsb2 484-pin fbga* pin number a3p400 function note: *refer to the "user i/o naming convention" section on page 2-44 .
proasic3 flash family fpgas 4-44 advanced v0.2 r17 gdb1/io78ppb1 r18 gdc1/io77pdb1 r19 io76ndb1 r20 v cc r21 nc r22 nc t1 nc t2 nc t3 nc t4 io141pdb3 t5 io131rsb2 t6 gec1/io137ppb3 t7 io128rsb2 t8 gndq t9 gea2/io134rsb2 t10 io113rsb2 t11 io109rsb2 t12 io100rsb2 t13 io95rsb2 t14 io90rsb2 t15 gndq t16 io83rsb2 t17 v jtag t18 gdc0/io77ndb1 t19 gda1/io79pdb1 t20 nc t21 nc t22 nc u1 nc u2 nc u3 nc u4 geb1/io136pdb3 u5 geb0/io136ndb3 u6 io130rsb2 u7 io129rsb2 u8 io126rsb2 484-pin fbga* pin number a3p400 function u9 io121rsb2 u10 io115rsb2 u11 io108rsb2 u12 io101rsb2 u13 io94rsb2 u14 io88rsb2 u15 io84rsb2 u16 tck u17 v pump u18 trst u19 gda0/io79ndb1 u20 nc u21 nc u22 nc v1 nc v2 nc v3 gnd v4 gea1/io135pdb3 v5 gea0/io135ndb3 v6 io125rsb2 v7 gec2/io132rsb2 v8 io122rsb2 v9 io118rsb2 v10 io112rsb2 v11 io107rsb2 v12 io102rsb2 v13 io96rsb2 v14 io91rsb2 v15 io87rsb2 v16 gdb2/io81rsb2 v17 tdi v18 nc v19 tdo v20 gnd v21 nc v22 nc 484-pin fbga* pin number a3p400 function w1 nc w2 nc w3 nc w4 gnd w5 io124rsb2 w6 geb2/io133rsb2 w7 io123rsb2 w8 io120rsb2 w9 io116rsb2 w10 io111rsb2 w11 io105rsb2 w12 io103rsb2 w13 io97rsb2 w14 io93rsb2 w15 gdc2/io82rsb2 w16 io86rsb2 w17 gda2/io80rsb2 w18 tms w19 gnd w20 nc w21 nc w22 nc y1 v cci b3 y2 nc y3 nc y4 nc y5 gnd y6 nc y7 nc y8 v cc y9 v cc y10 nc y11 nc y12 nc y13 nc y14 v cc 484-pin fbga* pin number a3p400 function note: *refer to the "user i/o naming convention" section on page 2-44 .
proasic3 flash family fpgas advanced v0.2 4-45 y15 v cc y16 nc y17 nc y18 gnd y19 nc y20 nc y21 nc y22 v cci b1 aa1 gnd aa2 v cci b3 aa3 nc aa4 nc aa5 nc aa6 nc aa7 nc aa8 nc aa9 nc aa10 nc aa11 nc aa12 nc aa13 nc aa14 nc aa15 nc aa16 nc aa17 nc aa18 nc aa19 nc aa20 nc aa21 v cci b1 aa22 gnd ab1 gnd ab2 gnd ab3 v cci b2 ab4 nc ab5 nc ab6 io119rsb2 484-pin fbga* pin number a3p400 function ab7 io117rsb2 ab8 io114rsb2 ab9 io110rsb2 ab10 nc ab11 nc ab12 io104rsb2 ab13 io98rsb2 ab14 nc ab15 nc ab16 io92rsb2 ab17 io89rsb2 ab18 nc ab19 nc ab20 v cci b2 ab21 gnd ab22 gnd 484-pin fbga* pin number a3p400 function note: *refer to the "user i/o naming convention" section on page 2-44 .
proasic3 flash family fpgas 4-46 advanced v0.2 484-pin fbga* pin number a3p600 function a1 gnd a2 gnd a3 v cci b0 a4 nc a5 nc a6 io08rsb0 a7 io09rsb0 a8 nc a9 nc a10 io21rsb0 a11 io23rsb0 a12 io27rsb0 a13 io28rsb0 a14 nc a15 nc a16 io35rsb0 a17 io45rsb0 a18 nc a19 nc a20 v cci b0 a21 gnd a22 gnd b1 gnd b2 v cci b3 b3 nc b4 nc b5 nc b6 io07rsb0 b7 io11rsb0 b8 nc b9 nc b10 io20rsb0 b11 nc b12 nc b13 io34rsb0 b14 nc b15 nc b16 io44rsb0 b17 io48rsb0 b18 nc b19 nc b20 nc b21 v cci b1 b22 gnd c1 v cci b3 c2 nc c3 nc c4 nc c5 gnd c6 nc c7 nc c8 v cc c9 v cc c10 nc c11 nc c12 nc c13 nc c14 v cc c15 v cc c16 nc c17 nc c18 gnd c19 nc c20 nc c21 nc c22 v cci b1 d1 nc d2 nc d3 nc d4 gnd d5 gaa0/io00rsb0 d6 gaa1/io01rsb0 484-pin fbga* pin number a3p600 function d7 gab0/io02rsb0 d8 io12rsb0 d9 io14rsb0 d10 io19rsb0 d11 io26rsb0 d12 io31rsb0 d13 io37rsb0 d14 io41rsb0 d15 io47rsb0 d16 gbb1/io57rsb0 d17 gba0/io58rsb0 d18 gba1/io59rsb0 d19 gnd d20 nc d21 nc d22 nc e1 nc e2 nc e3 gnd e4 gab2/io169pdb3 e5 gaa2/io170pdb3 e6 gndq e7 gab1/io03rsb0 e8 io10rsb0 e9 io15rsb0 e10 io18rsb0 e11 io24rsb0 e12 io32rsb0 e13 io40rsb0 e14 io43rsb0 e15 gbc1/io55rsb0 e16 gbb0/io56rsb0 e17 io49rsb0 e18 gba2/io60pdb1 e19 io60ndb1 e20 gnd 484-pin fbga* pin number a3p600 function note: *refer to the "user i/o naming convention" section on page 2-44 .
proasic3 flash family fpgas advanced v0.2 4-47 e21 nc e22 nc f1 nc f2 nc f3 nc f4 io169ndb3 f5 io170ndb3 f6 vmv3 f7 io06rsb0 f8 gac0/io04rsb0 f9 gac1/io05rsb0 f10 io17rsb0 f11 io25rsb0 f12 io33rsb0 f13 io38rsb0 f14 io42rsb0 f15 gbc0/io54rsb0 f16 io52rsb0 f17 io51rsb0 f18 io50rsb0 f19 io61npb1 f20 nc f21 nc f22 nc g1 io163ndb3 g2 io163pdb3 g3 nc g4 io166ndb3 g5 io166pdb3 g6 gac2/io168pdb3 g7 io168ndb3 g8 gndq g9 io13rsb0 g10 io16rsb0 g11 io22rsb0 g12 io36rsb0 484-pin fbga* pin number a3p600 function g13 io39rsb0 g14 io46rsb0 g15 gndq g16 io53rsb0 g17 gbb2/io61ppb1 g18 io63ppb1 g19 io65pdb1 g20 nc g21 nc g22 nc h1 nc h2 nc h3 v cc h4 io165ndb3 h5 io165pdb3 h6 io167pdb3 h7 io167ndb3 h8 vmv0 h9 v cci b0 h10 v cci b0 h11 io29rsb0 h12 io30rsb0 h13 v cci b0 h14 v cci b0 h15 vmv1 h16 gbc2/io62pdb1 h17 io63npb1 h18 io64ppb1 h19 io65ndb1 h20 v cc h21 nc h22 nc j1 io153pdb3 j2 io154ndb3 j3 nc j4 io154pdb3 484-pin fbga* pin number a3p600 function j5 io162ppb3 j6 io164pdb3 j7 io164ndb3 j8 v cci b3 j9 gnd j10 v cc j11 v cc j12 v cc j13 v cc j14 gnd j15 v cci b1 j16 io62ndb1 j17 io64npb1 j18 io66ppb1 j19 io67ppb1 j20 nc j21 io74pdb1 j22 io74ndb1 k1 io153ndb3 k2 nc k3 nc k4 io155ndb3 k5 io155pdb3 k6 io162npb3 k7 gfc1/io161ppb3 k8 v cci b3 k9 v cc k10 gnd k11 gnd k12 gnd k13 gnd k14 v cc k15 v cci b1 k16 gcc1/io68ppb1 k17 io66npb1 k18 io67npb1 484-pin fbga* pin number a3p600 function note: *refer to the "user i/o naming convention" section on page 2-44 .
proasic3 flash family fpgas 4-48 advanced v0.2 k19 io71npb1 k20 nc k21 nc k22 io75pdb1 l1 nc l2 io152pdb3 l3 nc l4 gfb0/io160npb3 l5 gfa0/io159ndb3 l6 gfb1/io160ppb3 l7 v complf l8 gfc0/io161npb3 l9 v cc l10 gnd l11 gnd l12 gnd l13 gnd l14 v cc l15 gcc0/io68npb1 l16 gcb1/io69ppb1 l17 gca0/io70npb1 l18 io73npb1 l19 gcb0/io69npb1 l20 nc l21 nc l22 io75ndb1 m1 nc m2 io152ndb3 m3 nc m4 gfa2/io158ppb3 m5 gfa1/io159pdb3 m6 v ccplf m7 io157ndb3 m8 gfb2/io157pdb3 m9 v cc m10 gnd 484-pin fbga* pin number a3p600 function m11 gnd m12 gnd m13 gnd m14 v cc m15 gcb2/io72ppb1 m16 gca1/io70ppb1 m17 gcc2/io73ppb1 m18 io77ppb1 m19 gca2/io71ppb1 m20 nc m21 io76pdb1 m22 nc n1 io150ppb3 n2 nc n3 nc n4 gfc2/io156ppb3 n5 io158npb3 n6 io151pdb3 n7 io151ndb3 n8 v cci b3 n9 v cc n10 gnd n11 gnd n12 gnd n13 gnd n14 v cc n15 v cci b1 n16 io72npb1 n17 io82pdb1 n18 io79pdb1 n19 io77npb1 n20 nc n21 io76ndb1 n22 nc p1 nc p2 io150npb3 484-pin fbga* pin number a3p600 function p3 nc p4 io149pdb3 p5 io156npb3 p6 io147pdb3 p7 io147ndb3 p8 v cci b3 p9 gnd p10 v cc p11 v cc p12 v cc p13 v cc p14 gnd p15 v cci b1 p16 gdb0/io85npb1 p17 io82ndb1 p18 io79ndb1 p19 io80pdb1 p20 nc p21 nc p22 io78pdb1 r1 nc r2 io148pdb3 r3 v cc r4 io149ndb3 r5 io146pdb3 r6 io146ndb3 r7 gec0/io144npb3 r8 vmv3 r9 v cci b2 r10 v cci b2 r11 io111rsb2 r12 io110rsb2 r13 v cci b2 r14 v cci b2 r15 vmv2 r16 io81ndb1 484-pin fbga* pin number a3p600 function note: *refer to the "user i/o naming convention" section on page 2-44 .
proasic3 flash family fpgas advanced v0.2 4-49 r17 gdb1/io85ppb1 r18 gdc1/io84pdb1 r19 io80ndb1 r20 v cc r21 io83pdb1 r22 io78ndb1 t1 nc t2 io148ndb3 t3 nc t4 io145pdb3 t5 io145ndb3 t6 gec1/io144ppb3 t7 io137rsb2 t8 gndq t9 gea2/io141rsb2 t10 io120rsb2 t11 io113rsb2 t12 io106rsb2 t13 io99rsb2 t14 io94rsb2 t15 gndq t16 io81pdb1 t17 v jtag t18 gdc0/io84ndb1 t19 gda1/io86pdb1 t20 nc t21 io83ndb1 t22 nc u1 nc u2 nc u3 nc u4 geb1/io143pdb3 u5 geb0/io143ndb3 u6 io138rsb2 u7 io135rsb2 u8 io134rsb2 484-pin fbga* pin number a3p600 function u9 io128rsb2 u10 io121rsb2 u11 io115rsb2 u12 io108rsb2 u13 io100rsb2 u14 io95rsb2 u15 vmv1 u16 tck u17 v pump u18 trst u19 gda0/io86ndb1 u20 nc u21 nc u22 nc v1 nc v2 nc v3 gnd v4 gea1/io142pdb3 v5 gea0/io142ndb3 v6 io136rsb2 v7 gec2/io139rsb2 v8 io130rsb2 v9 io125rsb2 v10 io119rsb2 v11 io114rsb2 v12 io107rsb2 v13 io101rsb2 v14 io96rsb2 v15 io90rsb2 v16 gdb2/io88rsb2 v17 tdi v18 gndq v19 tdo v20 gnd v21 nc v22 nc 484-pin fbga* pin number a3p600 function w1 nc w2 nc w3 nc w4 gnd w5 io133rsb2 w6 geb2/io140rsb2 w7 io132rsb2 w8 io127rsb2 w9 io123rsb2 w10 io117rsb2 w11 io112rsb2 w12 io109rsb2 w13 io102rsb2 w14 io97rsb2 w15 gdc2/io89rsb2 w16 io91rsb2 w17 gda2/io87rsb2 w18 tms w19 gnd w20 nc w21 nc w22 nc y1 v cci b3 y2 nc y3 nc y4 nc y5 gnd y6 nc y7 nc y8 v cc y9 v cc y10 nc y11 nc y12 nc y13 nc y14 v cc 484-pin fbga* pin number a3p600 function note: *refer to the "user i/o naming convention" section on page 2-44 .
proasic3 flash family fpgas 4-50 advanced v0.2 y15 v cc y16 nc y17 nc y18 gnd y19 nc y20 nc y21 nc y22 v cci b1 aa1 gnd aa2 v cci b3 aa3 nc aa4 nc aa5 nc aa6 io131rsb2 aa7 io126rsb2 aa8 nc aa9 nc aa10 io116rsb2 aa11 nc aa12 nc aa13 io103rsb2 aa14 nc aa15 nc aa16 io93rsb2 aa17 nc aa18 nc aa19 nc aa20 nc aa21 v cci b1 aa22 gnd ab1 gnd ab2 gnd ab3 v cci b2 ab4 nc ab5 nc ab6 io129rsb2 484-pin fbga* pin number a3p600 function ab7 io124rsb2 ab8 io122rsb2 ab9 io118rsb2 ab10 nc ab11 nc ab12 io105rsb2 ab13 io104rsb2 ab14 nc ab15 nc ab16 io98rsb2 ab17 io92rsb2 ab18 nc ab19 nc ab20 v cci b2 ab21 gnd ab22 gnd 484-pin fbga* pin number a3p600 function note: *refer to the "user i/o naming convention" section on page 2-44 .
proasic3 flash family fpgas advanced v0.2 4-51 484-pin fbga* pin number a3p1000 function a1 gnd a2 gnd a3 v cci b0 a4 io08rsb0 a5 io10rsb0 a6 io12rsb0 a7 io16rsb0 a8 io19rsb0 a9 io24rsb0 a10 io32rsb0 a11 io39rsb0 a12 io40rsb0 a13 io48rsb0 a14 io54rsb0 a15 io60rsb0 a16 io63rsb0 a17 io65rsb0 a18 io67rsb0 a19 nc a20 v cci b0 a21 gnd a22 gnd aa1 gnd aa2 v cci b3 aa3 nc aa4 io179rsb2 aa5 io174rsb2 aa6 io171rsb2 aa7 io165rsb2 aa8 io162rsb2 aa9 io157rsb2 aa10 io149rsb2 aa11 io142rsb2 aa12 io135rsb2 aa13 io129rsb2 aa14 nc aa15 nc aa16 io118rsb2 aa17 io115rsb2 aa18 nc aa19 nc aa20 nc aa21 v cci b1 aa22 gnd ab1 gnd ab2 gnd ab3 v cci b2 ab4 io175rsb2 ab5 io172rsb2 ab6 io168rsb2 ab7 io163rsb2 ab8 io161rsb2 ab9 io156rsb2 ab10 io147rsb2 ab11 io141rsb2 ab12 io140rsb2 ab13 io128rsb2 ab14 io123rsb2 ab15 io122rsb2 ab16 io120rsb2 ab17 io116rsb2 ab18 io114rsb2 ab19 nc ab20 v cci b2 ab21 gnd ab22 gnd b1 gnd b2 v cci b3 b3 nc b4 io07rsb0 b5 io09rsb0 b6 io11rsb0 484-pin fbga* pin number a3p1000 function b7 io14rsb0 b8 io18rsb0 b9 io23rsb0 b10 io30rsb0 b11 io37rsb0 b12 io41rsb0 b13 io49rsb0 b14 io55rsb0 b15 io61rsb0 b16 io64rsb0 b17 io66rsb0 b18 io68rsb0 b19 nc b20 nc b21 v cci b1 b22 gnd c1 v cci b3 c2 nc c3 nc c4 nc c5 gnd c6 nc c7 io13rsb0 c8 v cc c9 v cc c10 io29rsb0 c11 io36rsb0 c12 io42rsb0 c13 nc c14 v cc c15 v cc c16 nc c17 nc c18 gnd c19 nc c20 nc 484-pin fbga* pin number a3p1000 function note: *refer to the "user i/o naming convention" section on page 2-44 .
proasic3 flash family fpgas 4-52 advanced v0.2 c21 nc c22 v cci b1 d1 nc d2 nc d3 nc d4 gnd d5 gaa0/io00rsb0 d6 gaa1/io01rsb0 d7 gab0/io02rsb0 d8 io17rsb0 d9 io22rsb0 d10 io28rsb0 d11 io34rsb0 d12 io44rsb0 d13 io50rsb0 d14 io56rsb0 d15 io62rsb0 d16 gbb1/io75rsb0 d17 gba0/io76rsb0 d18 gba1/io77rsb0 d19 gnd d20 nc d21 nc d22 nc e1 nc e2 nc e3 gnd e4 gab2/io218pdb3 e5 gaa2/io219pdb3 e6 gndq e7 gab1/io03rsb0 e8 io15rsb0 e9 io20rsb0 e10 io26rsb0 e11 io35rsb0 e12 io45rsb0 484-pin fbga* pin number a3p1000 function e13 io52rsb0 e14 io57rsb0 e15 gbc1/io73rsb0 e16 gbb0/io74rsb0 e17 io69rsb0 e18 gba2/io78pdb1 e19 io78ndb1 e20 gnd e21 nc e22 nc f1 nc f2 io214ndb3 f3 io214pdb3 f4 io218ndb3 f5 io219ndb3 f6 vmv3 f7 io06rsb0 f8 gac0/io04rsb0 f9 gac1/io05rsb0 f10 io27rsb0 f11 io33rsb0 f12 io43rsb0 f13 io51rsb0 f14 io58rsb0 f15 gbc0/io72rsb0 f16 io70rsb0 f17 io71rsb0 f18 io81pdb1 f19 io81ndb1 f20 nc f21 nc f22 nc g1 io212ndb3 g2 io212pdb3 g3 nc g4 io215ndb3 484-pin fbga* pin number a3p1000 function g5 io215pdb3 g6 gac2/io217pdb3 g7 io217ndb3 g8 gndq g9 io21rsb0 g10 io25rsb0 g11 io31rsb0 g12 io46rsb0 g13 io53rsb0 g14 io59rsb0 g15 gndq g16 io80ndb1 g17 gbb2/io79pdb1 g18 io82pdb1 g19 io82ndb1 g20 io84pdb1 g21 io84ndb1 g22 nc h1 nc h2 nc h3 v cc h4 io210pdb3 h5 io213ndb3 h6 io213pdb3 h7 io216pdb3 h8 vmv0 h9 v cci b0 h10 v cci b0 h11 io38rsb0 h12 io47rsb0 h13 v cci b0 h14 v cci b0 h15 vmv1 h16 gbc2/io80pdb1 h17 io79ndb1 h18 io83pdb1 484-pin fbga* pin number a3p1000 function note: *refer to the "user i/o naming convention" section on page 2-44 .
proasic3 flash family fpgas advanced v0.2 4-53 h19 io83ndb1 h20 v cc h21 nc h22 nc j1 io209ndb3 j2 io209pdb3 j3 nc j4 io210ndb3 j5 io211ndb3 j6 io211pdb3 j7 io216ndb3 j8 v cci b3 j9 gnd j10 v cc j11 v cc j12 v cc j13 v cc j14 gnd j15 v cci b1 j16 io85pdb1 j17 io85ndb1 j18 io86pdb1 j19 io86ndb1 j20 nc j21 io95pdb1 j22 io95ndb1 k1 io207ndb3 k2 io207pdb3 k3 nc k4 io200ppb3 k5 io208ndb3 k6 io208pdb3 k7 gfc1/io206ppb3 k8 v cci b3 k9 v cc k10 gnd 484-pin fbga* pin number a3p1000 function k11 gnd k12 gnd k13 gnd k14 v cc k15 v cci b1 k16 gcc1/io88ppb1 k17 io87pdb1 k18 io87ndb1 k19 io94pdb1 k20 io94ndb1 k21 nc k22 io97pdb1 l1 nc l2 io199pdb3 l3 io200npb3 l4 gfb0/io205npb3 l5 gfa0/io204ndb3 l6 gfb1/io205ppb3 l7 v complf l8 gfc0/io206npb3 l9 v cc l10 gnd l11 gnd l12 gnd l13 gnd l14 v cc l15 gcc0/io88npb1 l16 gcb1/io89ppb1 l17 gca0/io90npb1 l18 io91npb1 l19 gcb0/io89npb1 l20 io96pdb1 l21 io96ndb1 l22 io97ndb1 m1 nc m2 io199ndb3 484-pin fbga* pin number a3p1000 function m3 io201npb3 m4 gfa2/io203ppb3 m5 gfa1/io204pdb3 m6 v ccplf m7 io202ndb3 m8 gfb2/io202pdb3 m9 v cc m10 gnd m11 gnd m12 gnd m13 gnd m14 v cc m15 gcb2/io92ppb1 m16 gca1/io90ppb1 m17 gcc2/io93pdb1 m18 io93ndb1 m19 gca2/io91ppb1 m20 io98pdb1 m21 io98ndb1 m22 nc n1 io198pdb3 n2 io198ndb3 n3 nc n4 gfc2/io201ppb3 n5 io203npb3 n6 io197pdb3 n7 io197ndb3 n8 v cci b3 n9 v cc n10 gnd n11 gnd n12 gnd n13 gnd n14 v cc n15 v cci b1 n16 io92npb1 484-pin fbga* pin number a3p1000 function note: *refer to the "user i/o naming convention" section on page 2-44 .
proasic3 flash family fpgas 4-54 advanced v0.2 n17 io100ndb1 n18 io100pdb1 n19 io102pdb1 n20 nc n21 io101pdb1 n22 io99pdb1 p1 nc p2 io196pdb3 p3 io196ndb3 p4 io195pdb3 p5 io195ndb3 p6 io194pdb3 p7 io194ndb3 p8 v cci b3 p9 gnd p10 v cc p11 v cc p12 v cc p13 v cc p14 gnd p15 v cci b1 p16 gdb0/io109npb1 p17 io103ndb1 p18 io103pdb1 p19 io102ndb1 p20 nc p21 io101ndb1 p22 io99ndb1 r1 nc r2 io193ppb3 r3 v cc r4 io191pdb3 r5 io190pdb3 r6 io190ndb3 r7 gec0/io187npb3 r8 vmv3 484-pin fbga* pin number a3p1000 function r9 v cci b2 r10 v cci b2 r11 io144rsb2 r12 io133rsb2 r13 v cci b2 r14 v cci b2 r15 vmv2 r16 io107pdb1 r17 gdb1/io109ppb1 r18 gdc1/io108pdb1 r19 io106ppb1 r20 v cc r21 io104ndb1 r22 io104pdb1 t1 io193npb3 t2 io192ppb3 t3 nc t4 io191ndb3 t5 io188ppb3 t6 gec1/io187ppb3 t7 io188npb3 t8 gndq t9 gea2/io184rsb2 t10 io153rsb2 t11 io146rsb2 t12 io134rsb2 t13 io126rsb2 t14 io121rsb2 t15 gndq t16 io107ndb1 t17 v jtag t18 gdc0/io108ndb1 t19 gda1/io110pdb1 t20 nc t21 io106npb1 t22 io105pdb1 484-pin fbga* pin number a3p1000 function u1 io192npb3 u2 io189pdb3 u3 io189ndb3 u4 geb1/io186pdb3 u5 geb0/io186ndb3 u6 io181rsb2 u7 io178rsb2 u8 io166rsb2 u9 io159rsb2 u10 io154rsb2 u11 io148rsb2 u12 io138rsb2 u13 io131rsb2 u14 io124rsb2 u15 vmv1 u16 tck u17 v pump u18 trst u19 gda0/io110ndb1 u20 nc u21 nc u22 io105ndb1 v1 nc v2 nc v3 gnd v4 gea1/io185pdb3 v5 gea0/io185ndb3 v6 io177rsb2 v7 gec2/io182rsb2 v8 io167rsb2 v9 io160rsb2 v10 io155rsb2 v11 io150rsb2 v12 io139rsb2 v13 io130rsb2 v14 io127rsb2 484-pin fbga* pin number a3p1000 function note: *refer to the "user i/o naming convention" section on page 2-44 .
proasic3 flash family fpgas advanced v0.2 4-55 v15 io119rsb2 v16 gdb2/io112rsb2 v17 tdi v18 gndq v19 tdo v20 gnd v21 nc v22 nc w1 nc w2 nc w3 nc w4 gnd w5 io176rsb2 w6 geb2/io183rsb2 w7 io170rsb2 w8 io164rsb2 w9 io158rsb2 w10 io152rsb2 w11 io145rsb2 w12 io137rsb2 w13 io132rsb2 w14 io125rsb2 w15 gdc2/io113rsb2 w16 io117rsb2 w17 gda2/io111rsb2 w18 tms w19 gnd w20 nc w21 nc w22 nc y1 v cci b3 y2 nc y3 nc y4 io180rsb2 y5 gnd y6 io173rsb2 484-pin fbga* pin number a3p1000 function y7 io169rsb2 y8 v cc y9 v cc y10 io151rsb2 y11 io143rsb2 y12 io136rsb2 y13 nc y14 v cc y15 v cc y16 nc y17 nc y18 gnd y19 nc y20 nc y21 nc y22 v cci b1 484-pin fbga* pin number a3p1000 function note: *refer to the "user i/o naming convention" section on page 2-44 .

proasic3 flash family fpgas advanced v0.2 5 -1 datasheet information datasheet categories in order to provide the latest information to designers, some datasheets are published before data has been fully characterized. datasheets are design ated as ?product brief,? ?advanced, ? ?production,? and ?web-only.? the definition of these categories are as follows: product brief the product brief is a summarized version of a advanced datasheet (advanced or production) containing general product information. this brief gives an overview of specific device and family information. advanced this datasheet version contains initial estimated information based on simulation, other products, devices, or speed grades. this information can be used as estimates, but not for production. datasheet supplement the datasheet supplement gives specific device information for a derivative family that differs from the general family datasheet. the supplement is to be used in conjunction with the datasheet to obtain more detailed information and for specifications th at do not differ between the two families. unmarked (production) this datasheet version contains informat ion that is considered to be final. international traffic in arms regulations (itar) and export administration regulations (ear) the products described in this datasheet are subject to the international traffic in arms regulations (itar) or the export administration regulations (ear). they may require an approved export lic ense prior to their export. an export can include a release or disclosure to a foreig n national inside or outs ide the united states.

51700012-1/1.05 http://www.actel.com actel and the actel logo are registered trademarks of actel corporation. all other trademarks are the property of their owners. actel corporation 2061 stierlin court mountain view, ca 94043-4655 usa phone 650.318.4200 fax 650.318.4600 actel europe ltd. dunlop house, riverside way camberley, surrey gu15 3yl united kingdom phone +44 (0) 1276 401 450 fax +44 (0) 1276 401 490 actel japan www.jp.actel.com exos ebisu bldg. 4f 1-24-14 ebisu shibuya-ku tokyo 150 japan phone +81.03.3445.7671 fax +81.03.3445.7668 actel hong kong www.actel.com.cn suite 2114, two pacific place 88 queensway, admiralty hong kong phone +852 2185 6460 fax +852 2185 6488

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